From patchwork Thu Jun 14 18:15:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 164988 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2F0A61007D1 for ; Fri, 15 Jun 2012 04:16:15 +1000 (EST) Received: from localhost ([::1]:41708 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfEab-0004Po-0M for incoming@patchwork.ozlabs.org; Thu, 14 Jun 2012 14:16:13 -0400 Received: from eggs.gnu.org ([208.118.235.92]:54550) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfEaQ-00048O-75 for qemu-devel@nongnu.org; Thu, 14 Jun 2012 14:16:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SfEaK-0007g7-Vu for qemu-devel@nongnu.org; Thu, 14 Jun 2012 14:16:01 -0400 Received: from mx1.redhat.com ([209.132.183.28]:5971) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfEaK-0007fq-MP for qemu-devel@nongnu.org; Thu, 14 Jun 2012 14:15:56 -0400 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q5EIFsMh026364 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 14 Jun 2012 14:15:55 -0400 Received: from bling.home (ovpn-116-19.ams2.redhat.com [10.36.116.19]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q5EIFqfF016050; Thu, 14 Jun 2012 14:15:53 -0400 From: Alex Williamson To: mst@redhat.com Date: Thu, 14 Jun 2012 12:15:51 -0600 Message-ID: <20120614181550.23440.39640.stgit@bling.home> In-Reply-To: <20120614181104.23440.62204.stgit@bling.home> References: <20120614181104.23440.62204.stgit@bling.home> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: jan.kiszka@siemens.com, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v3 1/8] msix: Add simple BAR allocation MSIX setup functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org msi_init() takes over a BAR without really specifying or allowing specification of how it does so. Instead, let's split it into two interfaces, one fully specified, and one trivially easy. This implements the latter. msix_init_exclusive_bar() takes over allocating and filling a PCI BAR _exclusively_ for the use of MSIX. When used, the matching msi_uninit_exclusive_bar() should be used to tear it down. Signed-off-by: Alex Williamson --- hw/msix.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ hw/msix.h | 3 +++ hw/pci.h | 2 ++ 3 files changed, 52 insertions(+) diff --git a/hw/msix.c b/hw/msix.c index b64f109..bafea94 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -299,6 +299,45 @@ err_config: return ret; } +int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries, + uint8_t bar_nr) +{ + int ret; + char *name; + + /* + * Migration compatibility dictates that this remains a 4k + * BAR with the vector table in the lower half and PBA in + * the upper half. Do not use these elsewhere! + */ +#define MSIX_EXCLUSIVE_BAR_SIZE 4096 +#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2) + + if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) { + return -EINVAL; + } + + if (asprintf(&name, "%s-msix", dev->name) == -1) { + return -ENOMEM; + } + + memory_region_init(&dev->msix_exclusive_bar, name, MSIX_EXCLUSIVE_BAR_SIZE); + + free(name); + + ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr, + MSIX_EXCLUSIVE_BAR_SIZE); + if (ret) { + memory_region_destroy(&dev->msix_exclusive_bar); + return ret; + } + + pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY, + &dev->msix_exclusive_bar); + + return 0; +} + static void msix_free_irq_entries(PCIDevice *dev) { int vector; @@ -329,6 +368,14 @@ int msix_uninit(PCIDevice *dev, MemoryRegion *bar) return 0; } +void msix_uninit_exclusive_bar(PCIDevice *dev) +{ + if (msix_present(dev)) { + msix_uninit(dev, &dev->msix_exclusive_bar); + memory_region_destroy(&dev->msix_exclusive_bar); + } +} + void msix_save(PCIDevice *dev, QEMUFile *f) { unsigned n = dev->msix_entries_nr; diff --git a/hw/msix.h b/hw/msix.h index 4a17f94..f681bb0 100644 --- a/hw/msix.h +++ b/hw/msix.h @@ -7,10 +7,13 @@ int msix_init(PCIDevice *pdev, unsigned short nentries, MemoryRegion *bar, unsigned bar_nr, unsigned bar_size); +int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries, + uint8_t bar_nr); void msix_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len); int msix_uninit(PCIDevice *d, MemoryRegion *bar); +void msix_uninit_exclusive_bar(PCIDevice *dev); unsigned int msix_nr_vectors_allocated(const PCIDevice *dev); diff --git a/hw/pci.h b/hw/pci.h index 4c96268..d517a54 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -226,6 +226,8 @@ struct PCIDevice { /* Space to store MSIX table */ uint8_t *msix_table_page; + /* MemoryRegion container for msix exclusive BAR setup */ + MemoryRegion msix_exclusive_bar; /* MMIO index used to map MSIX table and pending bit entries. */ MemoryRegion msix_mmio; /* Reference-count for entries actually in use by driver. */