Patchwork [arm] Remove obsolete FPA support (4/n): Remove Maverick patterns from MD files

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Submitter Richard Earnshaw
Date June 14, 2012, 4:49 p.m.
Message ID <4FDA162B.6000103@arm.com>
Download mbox | patch
Permalink /patch/164963/
State New
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Comments

Richard Earnshaw - June 14, 2012, 4:49 p.m.
This patch removes the define_insn and define_expand support for the
obsolete Maverick co-processor.

There's some necessary purging of code in arm.c as well (though the
major cleanups here are still to come).

Tested on arm-eabi and committed to trunk.

	* arm.c (arm_cirrus_insn_p): Delete.
	(cirrus_reorg): Delete.
	(arm_reorg): Don't call cirrus_reorg.
	(arm_final_prescan_insn_p): Don't check for cirrus insns.
	* arm.md (define_attr "type"): Remove mav_farith and mav_dmult.
	(adddi3, subdi3): Remove Maverick support.
	(arm_adddi3): Likewise.
	(adddi_sesidi_di, adddi_zesidi_di): Likewise.
	(addsf3, adddf3): Likewise.
	(subsf3, subdf3): Likewise.
	(mulsf3, muldf3): Likewise.
	(ashldi3, ashrdi3, lshrdi3): Likewise.
	(floatsisf2, floatsidf2): Likewise.
	(fix_truncsfsi2, fix_truncdfsi2): Likewise.
	(arm_movdi, thumb1_movdi_insn): Likewise.
	(arm_cmpdi_insn): Likewise.
	(cirrus_cmpsf, cirrus_cmpdf, cirrus_cmpdi): Likewise.
	(cirrus.md): Don't include.
	* cirrus.md: Delete file.
	* t-arm (MD_INCLUDES): Remove cirrus.md.

Patch

Index: config/arm/arm.c
===================================================================
--- config/arm/arm.c	(revision 188614)
+++ config/arm/arm.c	(working copy)
@@ -167,8 +167,6 @@  static int arm_address_cost (rtx, bool);
 static int arm_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
 static int arm_memory_move_cost (enum machine_mode, reg_class_t, bool);
 static bool arm_memory_load_p (rtx);
-static bool arm_cirrus_insn_p (rtx);
-static void cirrus_reorg (rtx);
 static void arm_init_builtins (void);
 static void arm_init_iwmmxt_builtins (void);
 static rtx safe_vector_operand (rtx, enum machine_mode);
@@ -9821,144 +9819,6 @@  arm_memory_load_p (rtx insn)
 	  || note_invalid_constants (insn, -1, false));
 }
 
-/* Return TRUE if INSN is a Cirrus instruction.  */
-static bool
-arm_cirrus_insn_p (rtx insn)
-{
-  enum attr_cirrus attr;
-
-  /* get_attr cannot accept USE or CLOBBER.  */
-  if (!insn
-      || GET_CODE (insn) != INSN
-      || GET_CODE (PATTERN (insn)) == USE
-      || GET_CODE (PATTERN (insn)) == CLOBBER)
-    return 0;
-
-  attr = get_attr_cirrus (insn);
-
-  return attr != CIRRUS_NOT;
-}
-
-/* Cirrus reorg for invalid instruction combinations.  */
-static void
-cirrus_reorg (rtx first)
-{
-  enum attr_cirrus attr;
-  rtx body = PATTERN (first);
-  rtx t;
-  int nops;
-
-  /* Any branch must be followed by 2 non Cirrus instructions.  */
-  if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
-    {
-      nops = 0;
-      t = next_nonnote_insn (first);
-
-      if (arm_cirrus_insn_p (t))
-	++ nops;
-
-      if (arm_cirrus_insn_p (next_nonnote_insn (t)))
-	++ nops;
-
-      while (nops --)
-	emit_insn_after (gen_nop (), first);
-
-      return;
-    }
-
-  /* (float (blah)) is in parallel with a clobber.  */
-  if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
-    body = XVECEXP (body, 0, 0);
-
-  if (GET_CODE (body) == SET)
-    {
-      rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
-
-      /* cfldrd, cfldr64, cfstrd, cfstr64 must
-	 be followed by a non Cirrus insn.  */
-      if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
-	{
-	  if (arm_cirrus_insn_p (next_nonnote_insn (first)))
-	    emit_insn_after (gen_nop (), first);
-
-	  return;
-	}
-      else if (arm_memory_load_p (first))
-	{
-	  unsigned int arm_regno;
-
-	  /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
-	     ldr/cfmv64hr combination where the Rd field is the same
-	     in both instructions must be split with a non Cirrus
-	     insn.  Example:
-
-	     ldr r0, blah
-	     nop
-	     cfmvsr mvf0, r0.  */
-
-	  /* Get Arm register number for ldr insn.  */
-	  if (GET_CODE (lhs) == REG)
-	    arm_regno = REGNO (lhs);
-	  else
-	    {
-	      gcc_assert (GET_CODE (rhs) == REG);
-	      arm_regno = REGNO (rhs);
-	    }
-
-	  /* Next insn.  */
-	  first = next_nonnote_insn (first);
-
-	  if (! arm_cirrus_insn_p (first))
-	    return;
-
-	  body = PATTERN (first);
-
-          /* (float (blah)) is in parallel with a clobber.  */
-          if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
-	    body = XVECEXP (body, 0, 0);
-
-	  if (GET_CODE (body) == FLOAT)
-	    body = XEXP (body, 0);
-
-	  if (get_attr_cirrus (first) == CIRRUS_MOVE
-	      && GET_CODE (XEXP (body, 1)) == REG
-	      && arm_regno == REGNO (XEXP (body, 1)))
-	    emit_insn_after (gen_nop (), first);
-
-	  return;
-	}
-    }
-
-  /* get_attr cannot accept USE or CLOBBER.  */
-  if (!first
-      || GET_CODE (first) != INSN
-      || GET_CODE (PATTERN (first)) == USE
-      || GET_CODE (PATTERN (first)) == CLOBBER)
-    return;
-
-  attr = get_attr_cirrus (first);
-
-  /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
-     must be followed by a non-coprocessor instruction.  */
-  if (attr == CIRRUS_COMPARE)
-    {
-      nops = 0;
-
-      t = next_nonnote_insn (first);
-
-      if (arm_cirrus_insn_p (t))
-	++ nops;
-
-      if (arm_cirrus_insn_p (next_nonnote_insn (t)))
-	++ nops;
-
-      while (nops --)
-	emit_insn_after (gen_nop (), first);
-
-      return;
-    }
-}
-
 /* Return TRUE if X references a SYMBOL_REF.  */
 int
 symbol_mentioned_p (rtx x)
@@ -13698,12 +13558,6 @@  arm_reorg (void)
   /* Scan all the insns and record the operands that will need fixing.  */
   for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
     {
-      if (TARGET_CIRRUS_FIX_INVALID_INSNS
-          && (arm_cirrus_insn_p (insn)
-	      || GET_CODE (insn) == JUMP_INSN
-	      || arm_memory_load_p (insn)))
-	cirrus_reorg (insn);
-
       if (GET_CODE (insn) == BARRIER)
 	push_minipool_barrier (insn, address);
       else if (INSN_P (insn))
@@ -18984,18 +18838,6 @@  arm_final_prescan_insn (rtx insn)
 		    || GET_CODE (scanbody) == PARALLEL)
 		  || get_attr_conds (this_insn) != CONDS_NOCOND)
 		fail = TRUE;
-
-	      /* A conditional cirrus instruction must be followed by
-		 a non Cirrus instruction.  However, since we
-		 conditionalize instructions in this function and by
-		 the time we get here we can't add instructions
-		 (nops), because shorten_branches() has already been
-		 called, we will disable conditionalizing Cirrus
-		 instructions to be safe.  */
-	      if (GET_CODE (scanbody) != USE
-		  && GET_CODE (scanbody) != CLOBBER
-		  && get_attr_cirrus (this_insn) != CIRRUS_NOT)
-		fail = TRUE;
 	      break;
 
 	    default:
Index: config/arm/t-arm
===================================================================
--- config/arm/t-arm	(revision 188616)
+++ config/arm/t-arm	(working copy)
@@ -29,7 +29,6 @@  MD_INCLUDES=	$(srcdir)/config/arm/arm102
 		$(srcdir)/config/arm/arm-fixed.md \
 		$(srcdir)/config/arm/arm-generic.md \
 		$(srcdir)/config/arm/arm-tune.md \
-		$(srcdir)/config/arm/cirrus.md \
 		$(srcdir)/config/arm/constraints.md \
 		$(srcdir)/config/arm/cortex-a15.md \
 		$(srcdir)/config/arm/cortex-a5.md \
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md	(revision 188616)
+++ config/arm/arm.md	(working copy)
@@ -348,13 +348,10 @@  (define_attr "insn"
 ; store2	store 2 words
 ; store3	store 3 words
 ; store4	store 4 (or more) words
-;  Additions for Cirrus Maverick co-processor:
-; mav_farith	Floating point arithmetic (4 cycle)
-; mav_dmult	Double multiplies (7 cycle)
 ;
 
 (define_attr "type"
-	"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
+	"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
 	(if_then_else 
 	 (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
 	 (const_string "mult")
@@ -577,8 +574,6 @@  (define_attr "generic_vfp" "yes,no"
 ;; Note: For DImode insns, there is normally no reason why operands should
 ;; not be in the same register, what we don't want is for something being
 ;; written to partially overlap something that is an input.
-;; Cirrus 64bit additions should not be split because we have a native
-;; 64bit addition instructions.
 
 (define_expand "adddi3"
  [(parallel
@@ -588,16 +583,6 @@  (define_expand "adddi3"
     (clobber (reg:CC CC_REGNUM))])]
   "TARGET_EITHER"
   "
-  if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
-    {
-      if (!cirrus_fp_register (operands[0], DImode))
-        operands[0] = force_reg (DImode, operands[0]);
-      if (!cirrus_fp_register (operands[1], DImode))
-        operands[1] = force_reg (DImode, operands[1]);
-      emit_insn (gen_cirrus_adddi3 (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-
   if (TARGET_THUMB1)
     {
       if (GET_CODE (operands[1]) != REG)
@@ -624,7 +609,7 @@  (define_insn_and_split "*arm_adddi3"
 	(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
 		 (match_operand:DI 2 "s_register_operand" "r,  0")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON"
+  "TARGET_32BIT && !TARGET_NEON"
   "#"
   "TARGET_32BIT && reload_completed
    && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))"
@@ -653,7 +638,7 @@  (define_insn_and_split "*adddi_sesidi_di
 		  (match_operand:SI 2 "s_register_operand" "r,r"))
 		 (match_operand:DI 1 "s_register_operand" "0,r")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+  "TARGET_32BIT"
   "#"
   "TARGET_32BIT && reload_completed"
   [(parallel [(set (reg:CC_C CC_REGNUM)
@@ -682,7 +667,7 @@  (define_insn_and_split "*adddi_zesidi_di
 		  (match_operand:SI 2 "s_register_operand" "r,r"))
 		 (match_operand:DI 1 "s_register_operand" "0,r")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+  "TARGET_32BIT"
   "#"
   "TARGET_32BIT && reload_completed"
   [(parallel [(set (reg:CC_C CC_REGNUM)
@@ -1078,9 +1063,6 @@  (define_expand "addsf3"
 		 (match_operand:SF 2 "arm_float_add_operand" "")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT"
   "
-  if (TARGET_MAVERICK
-      && !cirrus_fp_register (operands[2], SFmode))
-    operands[2] = force_reg (SFmode, operands[2]);
 ")
 
 (define_expand "adddf3"
@@ -1089,9 +1071,6 @@  (define_expand "adddf3"
 		 (match_operand:DF 2 "arm_float_add_operand" "")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
   "
-  if (TARGET_MAVERICK
-      && !cirrus_fp_register (operands[2], DFmode))
-    operands[2] = force_reg (DFmode, operands[2]);
 ")
 
 (define_expand "subdi3"
@@ -1102,15 +1081,6 @@  (define_expand "subdi3"
     (clobber (reg:CC CC_REGNUM))])]
   "TARGET_EITHER"
   "
-  if (TARGET_HARD_FLOAT && TARGET_MAVERICK
-      && TARGET_32BIT
-      && cirrus_fp_register (operands[0], DImode)
-      && cirrus_fp_register (operands[1], DImode))
-    {
-      emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-
   if (TARGET_THUMB1)
     {
       if (GET_CODE (operands[1]) != REG)
@@ -1325,13 +1295,6 @@  (define_expand "subsf3"
 		  (match_operand:SF 2 "arm_float_rhs_operand" "")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT"
   "
-  if (TARGET_MAVERICK)
-    {
-      if (!cirrus_fp_register (operands[1], SFmode))
-        operands[1] = force_reg (SFmode, operands[1]);
-      if (!cirrus_fp_register (operands[2], SFmode))
-        operands[2] = force_reg (SFmode, operands[2]);
-    }
 ")
 
 (define_expand "subdf3"
@@ -1340,13 +1303,6 @@  (define_expand "subdf3"
 		  (match_operand:DF 2 "arm_float_rhs_operand" "")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
   "
-  if (TARGET_MAVERICK)
-    {
-       if (!cirrus_fp_register (operands[1], DFmode))
-         operands[1] = force_reg (DFmode, operands[1]);
-       if (!cirrus_fp_register (operands[2], DFmode))
-         operands[2] = force_reg (DFmode, operands[2]);
-    }
 ")
 
 
@@ -1945,9 +1901,6 @@  (define_expand "mulsf3"
 		 (match_operand:SF 2 "arm_float_rhs_operand" "")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT"
   "
-  if (TARGET_MAVERICK
-      && !cirrus_fp_register (operands[2], SFmode))
-    operands[2] = force_reg (SFmode, operands[2]);
 ")
 
 (define_expand "muldf3"
@@ -1956,9 +1909,6 @@  (define_expand "muldf3"
 		 (match_operand:DF 2 "arm_float_rhs_operand" "")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
   "
-  if (TARGET_MAVERICK
-      && !cirrus_fp_register (operands[2], DFmode))
-    operands[2] = force_reg (DFmode, operands[2]);
 ")
 
 ;; Division insns
@@ -3514,8 +3464,7 @@  (define_expand "ashldi3"
                    (match_operand:SI 2 "reg_or_int_operand" "")))]
   "TARGET_32BIT"
   "
-  if (!CONST_INT_P (operands[2])
-      && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK)))
+  if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
     ; /* No special preparation statements; expand pattern as above.  */
   else
     {
@@ -3589,8 +3538,7 @@  (define_expand "ashrdi3"
                      (match_operand:SI 2 "reg_or_int_operand" "")))]
   "TARGET_32BIT"
   "
-  if (!CONST_INT_P (operands[2])
-      && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK)))
+  if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
     ; /* No special preparation statements; expand pattern as above.  */
   else
     {
@@ -3662,8 +3610,7 @@  (define_expand "lshrdi3"
                      (match_operand:SI 2 "reg_or_int_operand" "")))]
   "TARGET_32BIT"
   "
-  if (!CONST_INT_P (operands[2])
-      && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK)))
+  if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
     ; /* No special preparation statements; expand pattern as above.  */
   else
     {
@@ -4417,11 +4364,6 @@  (define_expand "floatsisf2"
 	(float:SF (match_operand:SI 1 "s_register_operand" "")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT"
   "
-  if (TARGET_MAVERICK)
-    {
-      emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
-      DONE;
-    }
 ")
 
 (define_expand "floatsidf2"
@@ -4429,11 +4371,6 @@  (define_expand "floatsidf2"
 	(float:DF (match_operand:SI 1 "s_register_operand" "")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
   "
-  if (TARGET_MAVERICK)
-    {
-      emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
-      DONE;
-    }
 ")
 
 (define_expand "fix_trunchfsi2"
@@ -4465,15 +4402,6 @@  (define_expand "fix_truncsfsi2"
 	(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand"  ""))))]
   "TARGET_32BIT && TARGET_HARD_FLOAT"
   "
-  if (TARGET_MAVERICK)
-    {
-      if (!cirrus_fp_register (operands[0], SImode))
-        operands[0] = force_reg (SImode, operands[0]);
-      if (!cirrus_fp_register (operands[1], SFmode))
-        operands[1] = force_reg (SFmode, operands[0]);
-      emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1]));
-      DONE;
-    }
 ")
 
 (define_expand "fix_truncdfsi2"
@@ -4481,13 +4409,6 @@  (define_expand "fix_truncdfsi2"
 	(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand"  ""))))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
   "
-  if (TARGET_MAVERICK)
-    {
-      if (!cirrus_fp_register (operands[1], DFmode))
-        operands[1] = force_reg (DFmode, operands[0]);
-      emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1]));
-      DONE;
-    }
 ")
 
 ;; Truncation insns
@@ -5341,7 +5262,7 @@  (define_insn "*arm_movdi"
   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
 	(match_operand:DI 1 "di_operand"              "rDa,Db,Dc,mi,r"))]
   "TARGET_32BIT
-   && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
+   && !(TARGET_HARD_FLOAT && TARGET_VFP)
    && !TARGET_IWMMXT
    && (   register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
@@ -5463,7 +5384,6 @@  (define_insn "*thumb1_movdi_insn"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r")
 	(match_operand:DI 1 "general_operand"      "l, I,J,>,l,mi,l,*r"))]
   "TARGET_THUMB1
-   && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
    && (   register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode))"
   "*
@@ -7664,7 +7584,7 @@  (define_insn "*arm_cmpdi_insn"
 	(compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r")
 			(match_operand:DI 1 "arm_di_operand"	   "rDi")))
    (clobber (match_scratch:SI 2 "=r"))]
-  "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+  "TARGET_32BIT"
   "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
   [(set_attr "conds" "set")
    (set_attr "length" "8")]
@@ -7701,38 +7621,6 @@  (define_insn "*thumb_cmpdi_zero"
    (set_attr "length" "2")]
 )
 
-;; Cirrus SF compare instruction
-(define_insn "*cirrus_cmpsf"
-  [(set (reg:CCFP CC_REGNUM)
-	(compare:CCFP (match_operand:SF 0 "cirrus_fp_register" "v")
-		      (match_operand:SF 1 "cirrus_fp_register" "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfcmps%?\\tr15, %V0, %V1"
-  [(set_attr "type"   "mav_farith")
-   (set_attr "cirrus" "compare")]
-)
-
-;; Cirrus DF compare instruction
-(define_insn "*cirrus_cmpdf"
-  [(set (reg:CCFP CC_REGNUM)
-	(compare:CCFP (match_operand:DF 0 "cirrus_fp_register" "v")
-		      (match_operand:DF 1 "cirrus_fp_register" "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfcmpd%?\\tr15, %V0, %V1"
-  [(set_attr "type"   "mav_farith")
-   (set_attr "cirrus" "compare")]
-)
-
-(define_insn "*cirrus_cmpdi"
-  [(set (reg:CC CC_REGNUM)
-	(compare:CC (match_operand:DI 0 "cirrus_fp_register" "v")
-		    (match_operand:DI 1 "cirrus_fp_register" "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfcmp64%?\\tr15, %V0, %V1"
-  [(set_attr "type"   "mav_farith")
-   (set_attr "cirrus" "compare")]
-)
-
 ; This insn allows redundant compares to be removed by cse, nothing should
 ; ever appear in the output file since (set (reg x) (reg x)) is a no-op that
 ; is deleted later on. The match_dup will match the mode here, so that
@@ -11406,8 +11294,6 @@  (define_expand "bswapsi2"
 
 ;; Load the load/store multiple patterns
 (include "ldmstm.md")
-;; Load the Maverick co-processor patterns
-(include "cirrus.md")
 ;; Vector bits common to IWMMXT and Neon
 (include "vec-common.md")
 ;; Load the Intel Wireless Multimedia Extension patterns
Index: config/arm/cirrus.md
===================================================================
--- config/arm/cirrus.md	(revision 188614)
+++ config/arm/cirrus.md	(working copy)
@@ -1,540 +0,0 @@ 
-;; CIRRUS EP9312 "Maverick" ARM floating point co-processor description.
-;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
-;; Contributed by Red Hat.
-;; Written by Aldy Hernandez (aldyh@redhat.com)
-
-;; This file is part of GCC.
-
-;; GCC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 3, or (at your option)
-;; any later version.
-
-;; GCC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3.  If not see
-;; <http://www.gnu.org/licenses/>.
-
-
-; Cirrus types for invalid insn combinations
-; not		Not a cirrus insn
-; normal	Any Cirrus insn not covered by the special cases below
-; double	cfldrd, cfldr64, cfstrd, cfstr64
-; compare	cfcmps, cfcmpd, cfcmp32, cfcmp64
-; move		cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr
-(define_attr "cirrus" "not,normal,double,compare,move" (const_string "not"))
-
-
-(define_insn "cirrus_adddi3"
-  [(set (match_operand:DI          0 "cirrus_fp_register" "=v")
-	(plus:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
-		 (match_operand:DI 2 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfadd64%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_addsi3"
-  [(set (match_operand:SI          0 "cirrus_fp_register" "=v")
-	(plus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
-		 (match_operand:SI 2 "cirrus_fp_register" "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfadd32%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_addsf3"
-  [(set (match_operand:SF          0 "cirrus_fp_register" "=v")
-	(plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
-		 (match_operand:SF 2 "cirrus_fp_register" "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfadds%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_adddf3"
-  [(set (match_operand:DF          0 "cirrus_fp_register" "=v")
-	(plus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
-		 (match_operand:DF 2 "cirrus_fp_register" "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfaddd%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_subdi3"
-  [(set (match_operand:DI           0 "cirrus_fp_register" "=v")
-	(minus:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
-		  (match_operand:DI 2 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfsub64%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_subsi3_insn"
-  [(set (match_operand:SI           0 "cirrus_fp_register" "=v")
-	(minus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
-		  (match_operand:SI 2 "cirrus_fp_register" "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfsub32%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_subsf3"
-  [(set (match_operand:SF           0 "cirrus_fp_register" "=v")
-	(minus:SF (match_operand:SF 1 "cirrus_fp_register"  "v")
-		  (match_operand:SF 2 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfsubs%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_subdf3"
-  [(set (match_operand:DF           0 "cirrus_fp_register" "=v")
-	(minus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
-		  (match_operand:DF 2 "cirrus_fp_register" "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfsubd%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_mulsi3"
-  [(set (match_operand:SI          0 "cirrus_fp_register" "=v")
-	(mult:SI (match_operand:SI 2 "cirrus_fp_register"  "v")
-		 (match_operand:SI 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfmul32%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "muldi3"
-  [(set (match_operand:DI          0 "cirrus_fp_register" "=v")
-	(mult:DI (match_operand:DI 2 "cirrus_fp_register"  "v")
-		 (match_operand:DI 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfmul64%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_dmult")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_mulsi3addsi"
-  [(set (match_operand:SI            0 "cirrus_fp_register" "=v")
-	(plus:SI
-	  (mult:SI (match_operand:SI 1 "cirrus_fp_register"  "v")
-		   (match_operand:SI 2 "cirrus_fp_register"  "v"))
-	  (match_operand:SI          3 "cirrus_fp_register"  "0")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfmac32%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-;; Cirrus SI multiply-subtract
-(define_insn "*cirrus_mulsi3subsi"
-  [(set (match_operand:SI            0 "cirrus_fp_register" "=v")
-	(minus:SI
-	  (match_operand:SI          1 "cirrus_fp_register"  "0")
-	  (mult:SI (match_operand:SI 2 "cirrus_fp_register"  "v")
-		   (match_operand:SI 3 "cirrus_fp_register"  "v"))))]
-  "0 && TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfmsc32%?\\t%V0, %V2, %V3"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_mulsf3"
-  [(set (match_operand:SF          0 "cirrus_fp_register" "=v")
-	(mult:SF (match_operand:SF 1 "cirrus_fp_register"  "v")
-		 (match_operand:SF 2 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfmuls%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_farith")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_muldf3"
-  [(set (match_operand:DF          0 "cirrus_fp_register" "=v")
-	(mult:DF (match_operand:DF 1 "cirrus_fp_register"  "v")
-		 (match_operand:DF 2 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfmuld%?\\t%V0, %V1, %V2"
-  [(set_attr "type" "mav_dmult")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashl_const"
-  [(set (match_operand:SI            0 "cirrus_fp_register" "=v")
-	(ashift:SI (match_operand:SI 1 "cirrus_fp_register"  "v")
-		   (match_operand:SI 2 "cirrus_shift_const"  "")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfsh32%?\\t%V0, %V1, #%s2"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashiftrt_const"
-  [(set (match_operand:SI	       0 "cirrus_fp_register" "=v")
-	(ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register"  "v")
-		     (match_operand:SI 2 "cirrus_shift_const"  "")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfsh32%?\\t%V0, %V1, #-%s2"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashlsi3"
-  [(set (match_operand:SI            0 "cirrus_fp_register" "=v")
-	(ashift:SI (match_operand:SI 1 "cirrus_fp_register"  "v")
-		   (match_operand:SI 2 "register_operand"    "r")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfrshl32%?\\t%V1, %V0, %s2"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "ashldi3_cirrus"
-  [(set (match_operand:DI            0 "cirrus_fp_register" "=v")
-	(ashift:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
-		   (match_operand:SI 2 "register_operand"    "r")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfrshl64%?\\t%V1, %V0, %s2"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashldi_const"
-  [(set (match_operand:DI            0 "cirrus_fp_register" "=v")
-	(ashift:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
-		   (match_operand:SI 2 "cirrus_shift_const"  "")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfsh64%?\\t%V0, %V1, #%s2"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashiftrtdi_const"
-  [(set (match_operand:DI            0 "cirrus_fp_register" "=v")
-	(ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register"  "v")
-		     (match_operand:SI 2 "cirrus_shift_const"  "")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfsh64%?\\t%V0, %V1, #-%s2"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_absdi2"
-  [(set (match_operand:DI         0 "cirrus_fp_register" "=v")
-	(abs:DI (match_operand:DI 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfabs64%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-;; This doesn't really clobber ``cc''.  Fixme: aldyh.  
-(define_insn "*cirrus_negdi2"
-  [(set (match_operand:DI         0 "cirrus_fp_register" "=v")
-	(neg:DI (match_operand:DI 1 "cirrus_fp_register"  "v")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfneg64%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_negsi2"
-  [(set (match_operand:SI         0 "cirrus_fp_register" "=v")
-	(neg:SI (match_operand:SI 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfneg32%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_negsf2"
-  [(set (match_operand:SF         0 "cirrus_fp_register" "=v")
-	(neg:SF (match_operand:SF 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfnegs%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_negdf2"
-  [(set (match_operand:DF         0 "cirrus_fp_register" "=v")
-	(neg:DF (match_operand:DF 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfnegd%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-;; This doesn't really clobber the condition codes either.  
-(define_insn "*cirrus_abssi2"
-  [(set (match_operand:SI         0 "cirrus_fp_register" "=v")
-        (abs:SI (match_operand:SI 1 "cirrus_fp_register"  "v")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
-  "cfabs32%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_abssf2"
-  [(set (match_operand:SF         0 "cirrus_fp_register" "=v")
-        (abs:SF (match_operand:SF 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfabss%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_absdf2"
-  [(set (match_operand:DF         0 "cirrus_fp_register" "=v")
-        (abs:DF (match_operand:DF 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfabsd%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-;; Convert Cirrus-SI to Cirrus-SF
-(define_insn "cirrus_floatsisf2"
-  [(set (match_operand:SF           0 "cirrus_fp_register" "=v")
- 	(float:SF (match_operand:SI 1 "s_register_operand"  "r")))
-   (clobber (match_scratch:DF 2 "=v"))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
-  [(set_attr "length" "8")
-   (set_attr "cirrus" "move")]
-)
-
-(define_insn "cirrus_floatsidf2"
-  [(set (match_operand:DF           0 "cirrus_fp_register" "=v")
-	(float:DF (match_operand:SI 1 "s_register_operand" "r")))
-   (clobber (match_scratch:DF 2 "=v"))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
-  [(set_attr "length" "8")
-   (set_attr "cirrus" "move")]
-)
-
-(define_insn "floatdisf2"
-  [(set (match_operand:SF           0 "cirrus_fp_register" "=v")
-	(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfcvt64s%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")])
-
-(define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
-	(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfcvt64d%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")])
-
-(define_insn "cirrus_truncsfsi2"
-  [(set (match_operand:SI         0 "s_register_operand" "=r")
-	(fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register"  "v"))))
-   (clobber (match_scratch:DF     2                      "=v"))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
-  [(set_attr "length" "8")
-   (set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_truncdfsi2"
-  [(set (match_operand:SI         0 "s_register_operand" "=r")
-	(fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register"  "v"))))
-   (clobber (match_scratch:DF     2                      "=v"))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
-  [(set_attr "length" "8")]
-)
-
-(define_insn "*cirrus_truncdfsf2"
-  [(set (match_operand:SF  0 "cirrus_fp_register" "=v")
-        (float_truncate:SF
-         (match_operand:DF 1 "cirrus_fp_register" "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfcvtds%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_extendsfdf2"
-  [(set (match_operand:DF                  0 "cirrus_fp_register" "=v")
-        (float_extend:DF (match_operand:SF 1 "cirrus_fp_register"  "v")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "cfcvtsd%?\\t%V0, %V1"
-  [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_arm_movdi"
-  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
-	(match_operand:DI 1 "di_operand"              "rIK,mi,r,r,v,mi,v,v"))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "*
-  {
-  switch (which_alternative)
-    {
-    case 0:
-      return \"#\";
-    case 1:
-    case 2:
-      return output_move_double (operands, true, NULL);
-
-    case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
-    case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
-
-    case 5: return \"cfldr64%?\\t%V0, %1\";
-    case 6: return \"cfstr64%?\\t%V1, %0\";
-
-    /* Shifting by 0 will just copy %1 into %0.  */
-    case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
-
-    default: gcc_unreachable ();
-    }
-  }"
-  [(set_attr "length"         "  8,   8,     8,   8,     8,     4,     4,     4")
-   (set_attr "type"           "  *,load2,store2,   *,     *,  load2,store2,     *")
-   (set_attr "pool_range"     "  *,1020,     *,   *,     *,  1020,     *,     *")
-   (set_attr "neg_pool_range" "  *,1012,     *,   *,     *,  1008,     *,     *")
-   (set_attr "cirrus"         "not, not,   not,move,normal,double,double,normal")]
-)
-
-;; Cirrus SI values have been outlawed.  Look in arm.h for the comment
-;; on HARD_REGNO_MODE_OK.
-
-(define_insn "*cirrus_movsf_hard_insn"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
-        (match_operand:SF 1 "general_operand"      "v,mE,r,v,v,r,mE,r"))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK
-   && (GET_CODE (operands[0]) != MEM
-       || register_operand (operands[1], SFmode))"
-  "@
-   cfcpys%?\\t%V0, %V1
-   cfldrs%?\\t%V0, %1
-   cfmvsr%?\\t%V0, %1
-   cfmvrs%?\\t%0, %V1
-   cfstrs%?\\t%V1, %0
-   mov%?\\t%0, %1
-   ldr%?\\t%0, %1\\t%@ float
-   str%?\\t%1, %0\\t%@ float"
-  [(set_attr "length"         "     *,     *,   *,     *,     *,  4,   4,     4")
-   (set_attr "type"           "     *,  load1,   *,     *,store1,  *,load1,store1")
-   (set_attr "pool_range"     "     *,   1020,   *,     *,     *,  *,4096,     *")
-   (set_attr "neg_pool_range" "     *,   1008,   *,     *,     *,  *,4084,     *")
-   (set_attr "cirrus"         "normal,normal,move,normal,normal,not, not,   not")]
-)
-
-(define_insn "*cirrus_movdf_hard_insn"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
-	(match_operand:DF 1 "general_operand"       "Q,r,r,r,mF,v,mF,r,v,v"))]
-  "TARGET_ARM
-   && TARGET_HARD_FLOAT && TARGET_MAVERICK
-   && (GET_CODE (operands[0]) != MEM
-       || register_operand (operands[1], DFmode))"
-  "*
-  {
-  switch (which_alternative)
-    {
-    case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
-    case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
-    case 2: return \"#\";
-    case 3: case 4: return output_move_double (operands, true, NULL);
-    case 5: return \"cfcpyd%?\\t%V0, %V1\";
-    case 6: return \"cfldrd%?\\t%V0, %1\";
-    case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
-    case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
-    case 9: return \"cfstrd%?\\t%V1, %0\";
-    default: gcc_unreachable ();
-    }
-  }"
-  [(set_attr "type"           "load1,store2,  *,store2,load1,     *,  load1,   *,     *,store2")
-   (set_attr "length"         "   4,     4,  8,     8,   8,     4,     4,   8,     8,     4")
-   (set_attr "pool_range"     "   *,     *,  *,     *, 252,     *,  1020,   *,     *,     *")
-   (set_attr "neg_pool_range" "   *,     *,  *,     *, 244,     *,  1008,   *,     *,     *")
-   (set_attr "cirrus"         " not,   not,not,   not, not,normal,double,move,normal,double")]
-)
-
-(define_insn "*cirrus_thumb2_movdi"
-  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
-	(match_operand:DI 1 "di_operand"              "rIK,mi,r,r,v,mi,v,v"))]
-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK"
-  "*
-  {
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-    case 2:
-      return (output_move_double (operands, true, NULL));
-
-    case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
-    case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
-
-    case 5: return \"cfldr64%?\\t%V0, %1\";
-    case 6: return \"cfstr64%?\\t%V1, %0\";
-
-    /* Shifting by 0 will just copy %1 into %0.  */
-    case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
-
-    default: abort ();
-    }
-  }"
-  [(set_attr "length"         "  8,   8,     8,   8,     8,     4,     4,     4")
-   (set_attr "type"           "  *,load2,store2,   *,     *,  load2,store2,     *")
-   (set_attr "pool_range"     "  *,4096,     *,   *,     *,  1020,     *,     *")
-   (set_attr "neg_pool_range" "  *,   0,     *,   *,     *,  1008,     *,     *")
-   (set_attr "cirrus"         "not, not,   not,move,normal,double,double,normal")]
-)
-
-(define_insn "*thumb2_cirrus_movsf_hard_insn"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
-        (match_operand:SF 1 "general_operand"      "v,mE,r,v,v,r,mE,r"))]
-  "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK
-   && (GET_CODE (operands[0]) != MEM
-       || register_operand (operands[1], SFmode))"
-  "@
-   cfcpys%?\\t%V0, %V1
-   cfldrs%?\\t%V0, %1
-   cfmvsr%?\\t%V0, %1
-   cfmvrs%?\\t%0, %V1
-   cfstrs%?\\t%V1, %0
-   mov%?\\t%0, %1
-   ldr%?\\t%0, %1\\t%@ float
-   str%?\\t%1, %0\\t%@ float"
-  [(set_attr "length"         "     *,     *,   *,     *,     *,  4,   4,     4")
-   (set_attr "type"           "     *,  load1,   *,     *,store1,  *,load1,store1")
-   (set_attr "pool_range"     "     *,   1020,   *,     *,     *,  *,4096,     *")
-   (set_attr "neg_pool_range" "     *,   1008,   *,     *,     *,  *,   0,     *")
-   (set_attr "cirrus"         "normal,normal,move,normal,normal,not, not,   not")]
-)
-
-(define_insn "*thumb2_cirrus_movdf_hard_insn"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
-	(match_operand:DF 1 "general_operand"       "Q,r,r,r,mF,v,mF,r,v,v"))]
-  "TARGET_THUMB2
-   && TARGET_HARD_FLOAT && TARGET_MAVERICK
-   && (GET_CODE (operands[0]) != MEM
-       || register_operand (operands[1], DFmode))"
-  "*
-  {
-  switch (which_alternative)
-    {
-    case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
-    case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
-    case 2: case 3: case 4: return output_move_double (operands, true, NULL);
-    case 5: return \"cfcpyd%?\\t%V0, %V1\";
-    case 6: return \"cfldrd%?\\t%V0, %1\";
-    case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
-    case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
-    case 9: return \"cfstrd%?\\t%V1, %0\";
-    default: abort ();
-    }
-  }"
-  [(set_attr "type"           "load1,store2,  *,store2,load1,     *,  load1,   *,     *,store2")
-   (set_attr "length"         "   4,     4,  8,     8,   8,     4,     4,   8,     8,     4")
-   (set_attr "pool_range"     "   *,     *,  *,     *,4092,     *,  1020,   *,     *,     *")
-   (set_attr "neg_pool_range" "   *,     *,  *,     *,   0,     *,  1008,   *,     *,     *")
-   (set_attr "cirrus"         " not,   not,not,   not, not,normal,double,move,normal,double")]
-)
-