From patchwork Thu Jun 14 05:59:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 164830 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 541321007D1 for ; Thu, 14 Jun 2012 16:06:52 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Sf38q-0000mx-8R; Thu, 14 Jun 2012 06:02:48 +0000 Received: from db3ehsobe006.messaging.microsoft.com ([213.199.154.144] helo=db3outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Sf36u-0008GB-Gy for linux-arm-kernel@lists.infradead.org; Thu, 14 Jun 2012 06:00:50 +0000 Received: from mail4-db3-R.bigfish.com (10.3.81.235) by DB3EHSOBE001.bigfish.com (10.3.84.21) with Microsoft SMTP Server id 14.1.225.23; Thu, 14 Jun 2012 05:59:40 +0000 Received: from mail4-db3 (localhost [127.0.0.1]) by mail4-db3-R.bigfish.com (Postfix) with ESMTP id 17E6F2E0534; Thu, 14 Jun 2012 05:59:40 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839hd24he5bhe96hf0ah) X-FB-DOMAIN-IP-MATCH: fail Received: from mail4-db3 (localhost.localdomain [127.0.0.1]) by mail4-db3 (MessageSwitch) id 1339653578743417_8006; Thu, 14 Jun 2012 05:59:38 +0000 (UTC) Received: from DB3EHSMHS005.bigfish.com (unknown [10.3.81.232]) by mail4-db3.bigfish.com (Postfix) with ESMTP id B31AD20044; Thu, 14 Jun 2012 05:59:38 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS005.bigfish.com (10.3.87.105) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 14 Jun 2012 05:59:36 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.298.5; Thu, 14 Jun 2012 01:00:27 -0500 Received: from S2101-09.ap.freescale.net ([10.192.185.88]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q5E5xmYq000483; Wed, 13 Jun 2012 23:00:24 -0700 From: Shawn Guo To: Subject: [PATCH 06/16] ARM: imx: move irq_domain_add_legacy call into avic driver Date: Thu, 14 Jun 2012 13:59:37 +0800 Message-ID: <1339653587-4832-7-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1339653587-4832-1-git-send-email-shawn.guo@linaro.org> References: <1339653587-4832-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.144 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Arnd Bergmann , Sascha Hauer , Rob Herring , Grant Likely , Shawn Guo , Dong Aisheng X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Move irq_domain_add_legacy call from imx27-dt.c into avic init function and have the avic driver adopt irqdomain support for both DT and non-DT boot. Now avic init function calls irq_alloc_descs to get irq_base and adds a lenacy irqdomain with the irq_base, so that the mapping between avic irq and Linux irq number can be handled by irqdomain. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/imx27-dt.c | 15 --------------- arch/arm/plat-mxc/avic.c | 26 +++++++++++++++++++------- 2 files changed, 19 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c index c734e56..5142ef0 100644 --- a/arch/arm/mach-imx/imx27-dt.c +++ b/arch/arm/mach-imx/imx27-dt.c @@ -10,7 +10,6 @@ */ #include -#include #include #include #include @@ -33,22 +32,8 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static int __init imx27_avic_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL); - return 0; -} - -static const struct of_device_id imx27_irq_match[] __initconst = { - { .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, }, - { /* sentinel */ } -}; - static void __init imx27_dt_init(void) { - of_irq_init(imx27_irq_match); - of_platform_populate(NULL, of_default_bus_match_table, imx27_auxdata_lookup, NULL); } diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index 689f81f..4fe1d9b 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c @@ -19,7 +19,9 @@ #include #include +#include #include +#include #include #include #include @@ -50,6 +52,7 @@ #define AVIC_NUM_IRQS 64 void __iomem *avic_base; +static struct irq_domain *domain; static u32 avic_saved_mask_reg[2]; @@ -108,7 +111,7 @@ static void avic_irq_suspend(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = gc->chip_types; - int idx = gc->irq_base >> 5; + int idx = d->hwirq >> 5; avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); __raw_writel(gc->wake_active, avic_base + ct->regs.mask); @@ -118,7 +121,7 @@ static void avic_irq_resume(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct irq_chip_type *ct = gc->chip_types; - int idx = gc->irq_base >> 5; + int idx = d->hwirq >> 5; __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); } @@ -128,11 +131,10 @@ static void avic_irq_resume(struct irq_data *d) #define avic_irq_resume NULL #endif -static __init void avic_init_gc(unsigned int irq_start) +static __init void avic_init_gc(int idx, unsigned int irq_start) { struct irq_chip_generic *gc; struct irq_chip_type *ct; - int idx = irq_start >> 5; gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, handle_level_irq); @@ -161,7 +163,7 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) if (nivector == 0xffff) break; - handle_IRQ(nivector, regs); + handle_IRQ(irq_find_mapping(domain, nivector), regs); } while (1); } @@ -172,6 +174,8 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) */ void __init mxc_init_irq(void __iomem *irqbase) { + struct device_node *np; + int irq_base; int i; avic_base = irqbase; @@ -190,8 +194,16 @@ void __init mxc_init_irq(void __iomem *irqbase) __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); - for (i = 0; i < AVIC_NUM_IRQS; i += 32) - avic_init_gc(i); + irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); + WARN_ON(irq_base < 0); + + np = of_find_compatible_node(NULL, NULL, "fsl,avic"); + domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, + &irq_domain_simple_ops, NULL); + WARN_ON(!domain); + + for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) + avic_init_gc(i, irq_base); /* Set default priority value (0) for all IRQ's */ for (i = 0; i < 8; i++)