Patchwork [U-Boot,v2,12/14] arm/km: support the 2 PCIe fpga resets

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Submitter Holger Brunck
Date June 13, 2012, 1:33 p.m.
Message ID <1339594400-4848-13-git-send-email-holger.brunck@keymile.com>
Download mbox | patch
Permalink /patch/164682/
State Superseded
Headers show

Comments

Holger Brunck - June 13, 2012, 1:33 p.m.
From: Valentin Longchamp <valentin.longchamp@keymile.com>

The PCIe FPGAs now have to support 2 resets: one for the non traffic
affecting part (PCIe) and one for the traffic affecting part.

When the FPGA is not reconfigured, we only reset the PCIe part.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
---
changes for v2:
  - nothing

 board/keymile/km_arm/fpga_config.c |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)

Patch

diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index 8ac6393..fcc5fe6 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -99,7 +99,7 @@  static int boco_set_bits(u8 reg, u8 flags)
 #define FPGA_INIT_B	0x10
 #define FPGA_DONE	0x20
 
-static int fpga_done()
+static int fpga_done(void)
 {
 	int ret = 0;
 	u8 regval;
@@ -206,25 +206,30 @@  int wait_for_fpga_config(void)
 }
 
 #define PRST1		0x4
-#define BRIDGE_RST	0x4
+#define PCIE_RST	0x10
+#define TRAFFIC_RST	0x04
 
 int fpga_reset(void)
 {
 	int ret = 0;
+	u8 resets;
 
 	if (!check_boco2()) {
 		/* we do not have BOCO2, this is not really used */
 		return 0;
 	}
 
-	ret = boco_clear_bits(PRST1, BRIDGE_RST);
+	/* if we have skipped, we only want to reset the PCIe part */
+	resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+	ret = boco_clear_bits(PRST1, resets);
 	if (ret)
 		return ret;
 
 	/* small delay for the pulse */
 	udelay(10);
 
-	ret = boco_set_bits(PRST1, BRIDGE_RST);
+	ret = boco_set_bits(PRST1, resets);
 	if (ret)
 		return ret;