| Submitter | Scott Wood |
|---|---|
| Date | June 12, 2012, 10:02 p.m. |
| Message ID | <20120612220232.GA17228@tyr.buserror.net> |
| Download | mbox | patch |
| Permalink | /patch/164509/ |
| State | New |
| Delegated to: | Benjamin Herrenschmidt |
| Headers | show |
Comments
On Tue, 2012-06-12 at 17:02 -0500, Scott Wood wrote: > It was branching to the cleanup part of the non-bolted handler, > which would have been bad if there were any chips with tlbsrx. > that use the bolted handler. Still relevant ? It doesn't apply anymore :-) Cheers, Ben. > Signed-off-by: Scott Wood <scott@tyr.buserror.net> > --- > arch/powerpc/mm/tlb_low_64e.S | 3 ++- > 1 files changed, 2 insertions(+), 1 deletions(-) > > diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S > index ff672bd..efe0f33 100644 > --- a/arch/powerpc/mm/tlb_low_64e.S > +++ b/arch/powerpc/mm/tlb_low_64e.S > @@ -128,7 +128,7 @@ BEGIN_MMU_FTR_SECTION > */ > PPC_TLBSRX_DOT(0,r16) > ldx r14,r14,r15 /* grab pgd entry */ > - beq normal_tlb_miss_done /* tlb exists already, bail */ > + beq tlb_miss_done_bolted /* tlb exists already, bail */ > MMU_FTR_SECTION_ELSE > ldx r14,r14,r15 /* grab pgd entry */ > ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) > @@ -184,6 +184,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) > mtspr SPRN_MAS7_MAS3,r15 > tlbwe > > +tlb_miss_done_bolted: > TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) > tlb_epilog_bolted > rfi
On 09/07/2012 02:34 PM, Scott Wood wrote: > On 09/06/2012 11:23 PM, Benjamin Herrenschmidt wrote: >> On Tue, 2012-06-12 at 17:02 -0500, Scott Wood wrote: >>> It was branching to the cleanup part of the non-bolted handler, >>> which would have been bad if there were any chips with tlbsrx. >>> that use the bolted handler. >> >> Still relevant ? It doesn't apply anymore :-) It's still relevant -- I'll respin. -Scott
Patch
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index ff672bd..efe0f33 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S @@ -128,7 +128,7 @@ BEGIN_MMU_FTR_SECTION */ PPC_TLBSRX_DOT(0,r16) ldx r14,r14,r15 /* grab pgd entry */ - beq normal_tlb_miss_done /* tlb exists already, bail */ + beq tlb_miss_done_bolted /* tlb exists already, bail */ MMU_FTR_SECTION_ELSE ldx r14,r14,r15 /* grab pgd entry */ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) @@ -184,6 +184,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) mtspr SPRN_MAS7_MAS3,r15 tlbwe +tlb_miss_done_bolted: TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) tlb_epilog_bolted rfi
It was branching to the cleanup part of the non-bolted handler, which would have been bad if there were any chips with tlbsrx. that use the bolted handler. Signed-off-by: Scott Wood <scott@tyr.buserror.net> --- arch/powerpc/mm/tlb_low_64e.S | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)