| Message ID | 1339535752-21565-1-git-send-email-mikhail.kshevetskiy@gmail.com |
|---|---|
| State | Deferred |
| Delegated to: | Tom Rini |
| Headers | show |
Hi Mikhail, On Tue, Jun 12, 2012 at 11:15 PM, Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> wrote: > follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of > OMAP-L138 DSP+ARM Processor Technical Reference Manual Thanks for fixing this! Just out of curiosity: Did you hit any problem or were you just comparing the code with the reference manual? > > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> > --- > arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 25 ++++++++++++++++------- > arch/arm/include/asm/arch-davinci/hardware.h | 1 + > 2 files changed, 19 insertions(+), 7 deletions(-) Acked-by: Christian Riesch <christian.riesch@omicron.at> For the calimain board Tested-by: Christian Riesch <christian.riesch@omicron.at> Regards, Christian
Hi Mikhail, On Tue, Jun 12, 2012 at 11:15 PM, Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> wrote: > follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of > OMAP-L138 DSP+ARM Processor Technical Reference Manual > > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Your patch causes a few checkpatch warnings, see below. > --- > arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 25 ++++++++++++++++------- > arch/arm/include/asm/arch-davinci/hardware.h | 1 + > 2 files changed, 19 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c > index df7d6a2..9682407 100644 > --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c > +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c > @@ -190,13 +190,21 @@ int da850_ddr_setup(void) > > setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); > setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); > - > - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); > } > - > + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); > writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); > - clrbits_le32(&davinci_syscfg1_regs->ddr_slew, > - (1 << DDR_SLEW_CMOSEN_BIT)); > + > + if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)){ missing whitespace before { > + /* DDR2 */ > + clrbits_le32(&davinci_syscfg1_regs->ddr_slew, > + (1 << DDR_SLEW_DDR_PDENA_BIT) | > + (1 << DDR_SLEW_CMOSEN_BIT)); > + }else{ missing whitespaces before and after "else". > + /* MOBILE DDR */ > + setbits_le32(&davinci_syscfg1_regs->ddr_slew, > + (1 << DDR_SLEW_DDR_PDENA_BIT) | > + (1 << DDR_SLEW_CMOSEN_BIT)); > + } > > /* > * SDRAM Configuration Register (SDCR): > @@ -216,7 +224,10 @@ int da850_ddr_setup(void) > writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); > > /* write memory configuration and timing */ > - writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); > + if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))){ missing whitespace before { Please fix these warnings and resubmit. Thank you! Regards, Christian > + /* MOBILE DDR only*/ > + writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); > + } > writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); > writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); > > @@ -240,7 +251,7 @@ int da850_ddr_setup(void) > > /* disable self refresh */ > clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, > - DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN); > + DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); > writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); > > return 0; > diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h > index b145c6e..56e5743 100644 > --- a/arch/arm/include/asm/arch-davinci/hardware.h > +++ b/arch/arm/include/asm/arch-davinci/hardware.h > @@ -505,6 +505,7 @@ struct davinci_syscfg1_regs { > ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE) > > #define DDR_SLEW_CMOSEN_BIT 4 > +#define DDR_SLEW_DDR_PDENA_BIT 5 > > #define VTP_POWERDWN (1 << 6) > #define VTP_LOCK (1 << 7) > -- > 1.7.10 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
On Thu, 21 Jun 2012 09:37:09 +0200 Christian Riesch <christian.riesch@omicron.at> wrote: > Hi Mikhail, > > On Tue, Jun 12, 2012 at 11:15 PM, Mikhail Kshevetskiy > <mikhail.kshevetskiy@gmail.com> wrote: > > follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of > > OMAP-L138 DSP+ARM Processor Technical Reference Manual > > Thanks for fixing this! Just out of curiosity: Did you hit any problem > or were you just comparing the code with the reference manual? Hard to say, I faced with memory initialization problem (caused by hardware bug). Before I hit a real problem, I study omap documentation and find disagreements with the code. So i just fix it. > > > > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> > > --- > > arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 25 ++++++++++++++++------- > > arch/arm/include/asm/arch-davinci/hardware.h | 1 + > > 2 files changed, 19 insertions(+), 7 deletions(-) > > Acked-by: Christian Riesch <christian.riesch@omicron.at> > > For the calimain board > > Tested-by: Christian Riesch <christian.riesch@omicron.at> > > Regards, Christian
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index df7d6a2..9682407 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -190,13 +190,21 @@ int da850_ddr_setup(void) setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); - - setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); } - + setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - clrbits_le32(&davinci_syscfg1_regs->ddr_slew, - (1 << DDR_SLEW_CMOSEN_BIT)); + + if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)){ + /* DDR2 */ + clrbits_le32(&davinci_syscfg1_regs->ddr_slew, + (1 << DDR_SLEW_DDR_PDENA_BIT) | + (1 << DDR_SLEW_CMOSEN_BIT)); + }else{ + /* MOBILE DDR */ + setbits_le32(&davinci_syscfg1_regs->ddr_slew, + (1 << DDR_SLEW_DDR_PDENA_BIT) | + (1 << DDR_SLEW_CMOSEN_BIT)); + } /* * SDRAM Configuration Register (SDCR): @@ -216,7 +224,10 @@ int da850_ddr_setup(void) writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); /* write memory configuration and timing */ - writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); + if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))){ + /* MOBILE DDR only*/ + writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); + } writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); @@ -240,7 +251,7 @@ int da850_ddr_setup(void) /* disable self refresh */ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, - DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN); + DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); return 0; diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index b145c6e..56e5743 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -505,6 +505,7 @@ struct davinci_syscfg1_regs { ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE) #define DDR_SLEW_CMOSEN_BIT 4 +#define DDR_SLEW_DDR_PDENA_BIT 5 #define VTP_POWERDWN (1 << 6) #define VTP_LOCK (1 << 7)
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of OMAP-L138 DSP+ARM Processor Technical Reference Manual Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> --- arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 25 ++++++++++++++++------- arch/arm/include/asm/arch-davinci/hardware.h | 1 + 2 files changed, 19 insertions(+), 7 deletions(-)