Patchwork [U-Boot] mx6: Avoid writing to read-only bits in imximage.cfg

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Submitter Vikram Narayanan
Date June 12, 2012, 2:50 p.m.
Message ID <4FD75739.90007@gmail.com>
Download mbox | patch
Permalink /patch/164425/
State Accepted
Commit b29da17494269c7e7f62eccc8ab78651a6c7b3d9
Delegated to: Stefano Babic
Headers show

Comments

Vikram Narayanan - June 12, 2012, 2:50 p.m.
If in case this is valid according to the latest datasheet, ignore this patch.

--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
bits 4 and 5 read-only and the value is always set as zero.
So write '0' to these bits instead of writing '1'.

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Dirk Behme <dirk.behme@googlemail.com>
---
 board/freescale/mx6qarm2/imximage.cfg      |    2 +-
 board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
Dirk Behme - June 12, 2012, 3:05 p.m.
On 12.06.2012 16:50, Vikram Narayanan wrote:
> If in case this is valid according to the latest datasheet, ignore this patch.
 >
> --
> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
> bits 4 and 5 read-only and the value is always set as zero.
> So write '0' to these bits instead of writing '1'.

Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)

Best regards

Dirk


> Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
> Cc: Jason Liu <r64343@freescale.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---
>  board/freescale/mx6qarm2/imximage.cfg      |    2 +-
>  board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
> index ceecbf9..bf941a3 100644
> --- a/board/freescale/mx6qarm2/imximage.cfg
> +++ b/board/freescale/mx6qarm2/imximage.cfg
> @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
>  DATA 4 0x020c4080 0x000003FF
>  
>  # enable AXI cache for VDOA/VPU/IPU
> -DATA 4 0x020e0010 0xF00000FF
> +DATA 4 0x020e0010 0xF00000CF
>  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
>  DATA 4 0x020e0018 0x007F007F
>  DATA 4 0x020e001c 0x007F007F
> diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg
> index c389427..62498ab 100644
> --- a/board/freescale/mx6qsabrelite/imximage.cfg
> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
> @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
>  DATA 4 0x020c4080 0x000003FF
>  
>  # enable AXI cache for VDOA/VPU/IPU
> -DATA 4 0x020e0010 0xF00000FF
> +DATA 4 0x020e0010 0xF00000CF
>  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
>  DATA 4 0x020e0018 0x007F007F
>  DATA 4 0x020e001c 0x007F007F
Liu Hui-R64343 - June 13, 2012, 2:55 a.m.
>-----Original Message-----
>From: Dirk Behme [mailto:dirk.behme@de.bosch.com]
>Sent: Tuesday, June 12, 2012 11:05 PM
>To: Fabio Estevam; Liu Hui-R64343
>Cc: Vikram Narayanan; u-boot@lists.denx.de
>Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
>imximage.cfg
>
>On 12.06.2012 16:50, Vikram Narayanan wrote:
>> If in case this is valid according to the latest datasheet, ignore this patch.
> >
>> --
>> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4
>> and 5 read-only and the value is always set as zero.
>> So write '0' to these bits instead of writing '1'.
>
>Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)

Yes, according to the RM, 
5
Reserved
This read-only field is reserved and always has the value 0.
4
Reserved
This read-only field is reserved and always has the value 0.

So, write 1 should have no effect.
 
>
>Best regards
>
>Dirk
>
>
>> Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
>> Cc: Jason Liu <r64343@freescale.com>
>> Cc: Dirk Behme <dirk.behme@googlemail.com>
>> ---
>>  board/freescale/mx6qarm2/imximage.cfg      |    2 +-
>>  board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/board/freescale/mx6qarm2/imximage.cfg
>> b/board/freescale/mx6qarm2/imximage.cfg
>> index ceecbf9..bf941a3 100644
>> --- a/board/freescale/mx6qarm2/imximage.cfg
>> +++ b/board/freescale/mx6qarm2/imximage.cfg
>> @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3  DATA 4
>0x020c4080
>> 0x000003FF
>>
>>  # enable AXI cache for VDOA/VPU/IPU
>> -DATA 4 0x020e0010 0xF00000FF
>> +DATA 4 0x020e0010 0xF00000CF
>>  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7  DATA 4 0x020e0018
>> 0x007F007F  DATA 4 0x020e001c 0x007F007F diff --git
>> a/board/freescale/mx6qsabrelite/imximage.cfg
>> b/board/freescale/mx6qsabrelite/imximage.cfg
>> index c389427..62498ab 100644
>> --- a/board/freescale/mx6qsabrelite/imximage.cfg
>> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
>> @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3  DATA 4
>0x020c4080
>> 0x000003FF
>>
>>  # enable AXI cache for VDOA/VPU/IPU
>> -DATA 4 0x020e0010 0xF00000FF
>> +DATA 4 0x020e0010 0xF00000CF
>>  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7  DATA 4 0x020e0018
>> 0x007F007F  DATA 4 0x020e001c 0x007F007F
Marek Vasut - June 13, 2012, 11:18 a.m.
Dear Liu Hui-R64343,

> >-----Original Message-----
> >From: Dirk Behme [mailto:dirk.behme@de.bosch.com]
> >Sent: Tuesday, June 12, 2012 11:05 PM
> >To: Fabio Estevam; Liu Hui-R64343
> >Cc: Vikram Narayanan; u-boot@lists.denx.de
> >Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
> >imximage.cfg
> >
> >On 12.06.2012 16:50, Vikram Narayanan wrote:
> >> If in case this is valid according to the latest datasheet, ignore this
> >> patch.
> >> 
> >> --
> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4
> >> and 5 read-only and the value is always set as zero.
> >> So write '0' to these bits instead of writing '1'.
> >
> >Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)
> 
> Yes, according to the RM,
> 5
> Reserved
> This read-only field is reserved and always has the value 0.
> 4
> Reserved
> This read-only field is reserved and always has the value 0.
> 
> So, write 1 should have no effect.

I really dislike how "write 1 should have no effect" sounds. Can you please 
check with HW people?

[..]

Best regards,
Marek Vasut
Fabio Estevam - June 13, 2012, 11:28 a.m.
On Wed, Jun 13, 2012 at 8:18 AM, Marek Vasut <marex@denx.de> wrote:

>
> I really dislike how "write 1 should have no effect" sounds. Can you please
> check with HW people?

I agree.

Jason, please check this with the design team.

Vikram's patch look correct.

Regards,

Fabio Estevam
Liu Hui-R64343 - June 13, 2012, 11:31 a.m.
Hi, Marek,

>-----Original Message-----
>From: Marek Vasut [mailto:marex@denx.de]
>Sent: Wednesday, June 13, 2012 7:18 PM
>To: u-boot@lists.denx.de
>Cc: Liu Hui-R64343; Dirk Behme; Fabio Estevam
>Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
>imximage.cfg
>
>Dear Liu Hui-R64343,
>
>> >-----Original Message-----
>> >From: Dirk Behme [mailto:dirk.behme@de.bosch.com]
>> >Sent: Tuesday, June 12, 2012 11:05 PM
>> >To: Fabio Estevam; Liu Hui-R64343
>> >Cc: Vikram Narayanan; u-boot@lists.denx.de
>> >Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
>> >imximage.cfg
>> >
>> >On 12.06.2012 16:50, Vikram Narayanan wrote:
>> >> If in case this is valid according to the latest datasheet, ignore
>> >> this patch.
>> >>
>> >> --
>> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits
>> >> 4 and 5 read-only and the value is always set as zero.
>> >> So write '0' to these bits instead of writing '1'.
>> >
>> >Jason, Fabio: What do you think? You should be the datasheet
>> >'masters' ;)
>>
>> Yes, according to the RM,
>> 5
>> Reserved
>> This read-only field is reserved and always has the value 0.
>> 4
>> Reserved
>> This read-only field is reserved and always has the value 0.
>>
>> So, write 1 should have no effect.
>
>I really dislike how "write 1 should have no effect" sounds. Can you please
>check with HW people?

Since this is read-only bit, if you write 1 to it, it will have no effect.

Yes, to avoid the confusion, for example to do the read-back check, I agree
with not writing '1' to the read-only bit. 

>
>[..]
>
>Best regards,
>Marek Vasut
Marek Vasut - June 13, 2012, 12:24 p.m.
Dear Liu Hui-R64343,

[...]

> >> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits
> >> >> 4 and 5 read-only and the value is always set as zero.
> >> >> So write '0' to these bits instead of writing '1'.
> >> >
> >> >Jason, Fabio: What do you think? You should be the datasheet
> >> >'masters' ;)
> >> 
> >> Yes, according to the RM,
> >> 5
> >> Reserved
> >> This read-only field is reserved and always has the value 0.
> >> 4
> >> Reserved
> >> This read-only field is reserved and always has the value 0.
> >> 
> >> So, write 1 should have no effect.
> >
> >I really dislike how "write 1 should have no effect" sounds. Can you
> >please check with HW people?
> 
> Since this is read-only bit, if you write 1 to it, it will have no effect.

For how long do you work with hardware? Did it never occur to you that when you 
wrote 1 to an "reserved" bit, it either did something you didn't expect or you 
had to rework it later because the new CPU has that bit for something else?

> Yes, to avoid the confusion, for example to do the read-back check, I agree
> with not writing '1' to the read-only bit.

Please, ask the hardware people about this.

> >[..]
> >
> >Best regards,
> >Marek Vasut

Best regards,
Marek Vasut
Marek Vasut - June 13, 2012, 12:27 p.m.
Dear Vikram Narayanan,

> If in case this is valid according to the latest datasheet, ignore this
> patch.
> 
> --
> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
> bits 4 and 5 read-only and the value is always set as zero.
> So write '0' to these bits instead of writing '1'.

I'm acking this as writing 0 to read-only bits is the only rightous thing to do. 
btw. how did you find this? Good catch, praise on you :-)

Acked-by: Marek Vasut <marex@denx.de>

> Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
> Cc: Jason Liu <r64343@freescale.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---
>  board/freescale/mx6qarm2/imximage.cfg      |    2 +-
>  board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/freescale/mx6qarm2/imximage.cfg
> b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
> --- a/board/freescale/mx6qarm2/imximage.cfg
> +++ b/board/freescale/mx6qarm2/imximage.cfg
> @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
>  DATA 4 0x020c4080 0x000003FF
> 
>  # enable AXI cache for VDOA/VPU/IPU
> -DATA 4 0x020e0010 0xF00000FF
> +DATA 4 0x020e0010 0xF00000CF
>  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
>  DATA 4 0x020e0018 0x007F007F
>  DATA 4 0x020e001c 0x007F007F
> diff --git a/board/freescale/mx6qsabrelite/imximage.cfg
> b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644
> --- a/board/freescale/mx6qsabrelite/imximage.cfg
> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
> @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
>  DATA 4 0x020c4080 0x000003FF
> 
>  # enable AXI cache for VDOA/VPU/IPU
> -DATA 4 0x020e0010 0xF00000FF
> +DATA 4 0x020e0010 0xF00000CF
>  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
>  DATA 4 0x020e0018 0x007F007F
>  DATA 4 0x020e001c 0x007F007F

Best regards,
Marek Vasut
Liu Hui-R64343 - June 13, 2012, 1:15 p.m.
Hi, Marek,

>-----Original Message-----
>From: Marek Vasut [mailto:marex@denx.de]
>Sent: Wednesday, June 13, 2012 8:25 PM
>To: u-boot@lists.denx.de
>Cc: Liu Hui-R64343; Dirk Behme
>Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
>imximage.cfg
>
>Dear Liu Hui-R64343,
>
>[...]
>
>> >> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
>> >> >> bits
>> >> >> 4 and 5 read-only and the value is always set as zero.
>> >> >> So write '0' to these bits instead of writing '1'.
>> >> >
>> >> >Jason, Fabio: What do you think? You should be the datasheet
>> >> >'masters' ;)
>> >>
>> >> Yes, according to the RM,
>> >> 5
>> >> Reserved
>> >> This read-only field is reserved and always has the value 0.
>> >> 4
>> >> Reserved
>> >> This read-only field is reserved and always has the value 0.
>> >>
>> >> So, write 1 should have no effect.
>> >
>> >I really dislike how "write 1 should have no effect" sounds. Can you
>> >please check with HW people?
>>
>> Since this is read-only bit, if you write 1 to it, it will have no effect.
>
>For how long do you work with hardware? Did it never occur to you that
>when you wrote 1 to an "reserved" bit, it either did something you didn't
>expect or you had to rework it later because the new CPU has that bit for
>something else?
>
>> Yes, to avoid the confusion, for example to do the read-back check, I
>> agree with not writing '1' to the read-only bit.
>
>Please, ask the hardware people about this.

Yes, I will and back to you.

>
>> >[..]
>> >
>> >Best regards,
>> >Marek Vasut
>
>Best regards,
>Marek Vasut
Marek Vasut - June 13, 2012, 1:21 p.m.
Dear Liu Hui-R64343,

> Hi, Marek,
> 
> >-----Original Message-----
> >From: Marek Vasut [mailto:marex@denx.de]
> >Sent: Wednesday, June 13, 2012 8:25 PM
> >To: u-boot@lists.denx.de
> >Cc: Liu Hui-R64343; Dirk Behme
> >Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
> >imximage.cfg
> >
> >Dear Liu Hui-R64343,
> >
> >[...]
> >
> >> >> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
> >> >> >> bits
> >> >> >> 4 and 5 read-only and the value is always set as zero.
> >> >> >> So write '0' to these bits instead of writing '1'.
> >> >> >
> >> >> >Jason, Fabio: What do you think? You should be the datasheet
> >> >> >'masters' ;)
> >> >> 
> >> >> Yes, according to the RM,
> >> >> 5
> >> >> Reserved
> >> >> This read-only field is reserved and always has the value 0.
> >> >> 4
> >> >> Reserved
> >> >> This read-only field is reserved and always has the value 0.
> >> >> 
> >> >> So, write 1 should have no effect.
> >> >
> >> >I really dislike how "write 1 should have no effect" sounds. Can you
> >> >please check with HW people?
> >> 
> >> Since this is read-only bit, if you write 1 to it, it will have no
> >> effect.
> >
> >For how long do you work with hardware? Did it never occur to you that
> >when you wrote 1 to an "reserved" bit, it either did something you didn't
> >expect or you had to rework it later because the new CPU has that bit for
> >something else?
> >
> >> Yes, to avoid the confusion, for example to do the read-back check, I
> >> agree with not writing '1' to the read-only bit.
> >
> >Please, ask the hardware people about this.
> 
> Yes, I will and back to you.

Thanks!

btw. sorry, I didn't meant to offend you.

Best regards,
Marek Vasut
Vikram Narayanan - June 13, 2012, 4:38 p.m.
Hello Marek,

On 6/13/2012 5:57 PM, Marek Vasut wrote:
> Dear Vikram Narayanan,
>
>> If in case this is valid according to the latest datasheet, ignore this
>> patch.
>>
>> --
>> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
>> bits 4 and 5 read-only and the value is always set as zero.
>> So write '0' to these bits instead of writing '1'.
>
> I'm acking this as writing 0 to read-only bits is the only rightous thing to do.
> btw. how did you find this? Good catch, praise on you :-)

:)
In the middle of writing a imximage.cfg file for a custom mx6 board.

Regards,
Vikram


> Acked-by: Marek Vasut<marex@denx.de>
>
>> Signed-off-by: Vikram Narayanan<vikram186@gmail.com>
>> Cc: Jason Liu<r64343@freescale.com>
>> Cc: Dirk Behme<dirk.behme@googlemail.com>
>> ---
>>   board/freescale/mx6qarm2/imximage.cfg      |    2 +-
>>   board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
>>   2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/board/freescale/mx6qarm2/imximage.cfg
>> b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
>> --- a/board/freescale/mx6qarm2/imximage.cfg
>> +++ b/board/freescale/mx6qarm2/imximage.cfg
>> @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
>>   DATA 4 0x020c4080 0x000003FF
>>
>>   # enable AXI cache for VDOA/VPU/IPU
>> -DATA 4 0x020e0010 0xF00000FF
>> +DATA 4 0x020e0010 0xF00000CF
>>   # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
>>   DATA 4 0x020e0018 0x007F007F
>>   DATA 4 0x020e001c 0x007F007F
>> diff --git a/board/freescale/mx6qsabrelite/imximage.cfg
>> b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644
>> --- a/board/freescale/mx6qsabrelite/imximage.cfg
>> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
>> @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
>>   DATA 4 0x020c4080 0x000003FF
>>
>>   # enable AXI cache for VDOA/VPU/IPU
>> -DATA 4 0x020e0010 0xF00000FF
>> +DATA 4 0x020e0010 0xF00000CF
>>   # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
>>   DATA 4 0x020e0018 0x007F007F
>>   DATA 4 0x020e001c 0x007F007F
>
> Best regards,
> Marek Vasut
Marek Vasut - June 13, 2012, 5:15 p.m.
Dear Vikram Narayanan,

> Hello Marek,
> 
> On 6/13/2012 5:57 PM, Marek Vasut wrote:
> > Dear Vikram Narayanan,
> > 
> >> If in case this is valid according to the latest datasheet, ignore this
> >> patch.
> >> 
> >> --
> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
> >> bits 4 and 5 read-only and the value is always set as zero.
> >> So write '0' to these bits instead of writing '1'.
> > 
> > I'm acking this as writing 0 to read-only bits is the only rightous thing
> > to do. btw. how did you find this? Good catch, praise on you :-)
> :
> :)
> 
> In the middle of writing a imximage.cfg file for a custom mx6 board.

So it did manifest somehow?

> Regards,
> Vikram
> 
> > Acked-by: Marek Vasut<marex@denx.de>
> > 
> >> Signed-off-by: Vikram Narayanan<vikram186@gmail.com>
> >> Cc: Jason Liu<r64343@freescale.com>
> >> Cc: Dirk Behme<dirk.behme@googlemail.com>
> >> ---
> >> 
> >>   board/freescale/mx6qarm2/imximage.cfg      |    2 +-
> >>   board/freescale/mx6qsabrelite/imximage.cfg |    2 +-
> >>   2 files changed, 2 insertions(+), 2 deletions(-)
> >> 
> >> diff --git a/board/freescale/mx6qarm2/imximage.cfg
> >> b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
> >> --- a/board/freescale/mx6qarm2/imximage.cfg
> >> +++ b/board/freescale/mx6qarm2/imximage.cfg
> >> @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3
> >> 
> >>   DATA 4 0x020c4080 0x000003FF
> >>   
> >>   # enable AXI cache for VDOA/VPU/IPU
> >> 
> >> -DATA 4 0x020e0010 0xF00000FF
> >> +DATA 4 0x020e0010 0xF00000CF
> >> 
> >>   # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
> >>   DATA 4 0x020e0018 0x007F007F
> >>   DATA 4 0x020e001c 0x007F007F
> >> 
> >> diff --git a/board/freescale/mx6qsabrelite/imximage.cfg
> >> b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab
> >> 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg
> >> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
> >> @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3
> >> 
> >>   DATA 4 0x020c4080 0x000003FF
> >>   
> >>   # enable AXI cache for VDOA/VPU/IPU
> >> 
> >> -DATA 4 0x020e0010 0xF00000FF
> >> +DATA 4 0x020e0010 0xF00000CF
> >> 
> >>   # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
> >>   DATA 4 0x020e0018 0x007F007F
> >>   DATA 4 0x020e001c 0x007F007F
> > 
> > Best regards,
> > Marek Vasut

Best regards,
Marek Vasut
Vikram Narayanan - June 13, 2012, 5:40 p.m.
Hello Marek,

On 6/13/2012 10:45 PM, Marek Vasut wrote:
> Dear Vikram Narayanan,
>
>> Hello Marek,
>>
>> On 6/13/2012 5:57 PM, Marek Vasut wrote:
>>> Dear Vikram Narayanan,
>>>
>>>> If in case this is valid according to the latest datasheet, ignore this
>>>> patch.
>>>>
>>>> --
>>>> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
>>>> bits 4 and 5 read-only and the value is always set as zero.
>>>> So write '0' to these bits instead of writing '1'.
>>>
>>> I'm acking this as writing 0 to read-only bits is the only rightous thing
>>> to do. btw. how did you find this? Good catch, praise on you :-)
>> :
>> :)
>>
>> In the middle of writing a imximage.cfg file for a custom mx6 board.
>
> So it did manifest somehow?

Still in progress. :)

Regards,
Vikram
Stefano Babic - June 15, 2012, 2:27 p.m.
On 12/06/2012 16:50, Vikram Narayanan wrote:
> If in case this is valid according to the latest datasheet, ignore this patch.
> 
> --
> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
> bits 4 and 5 read-only and the value is always set as zero.
> So write '0' to these bits instead of writing '1'.
> 
> Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
> Cc: Jason Liu <r64343@freescale.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Patch

diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index ceecbf9..bf941a3 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -167,7 +167,7 @@  DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
 # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg
index c389427..62498ab 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -164,7 +164,7 @@  DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
 
 # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
 # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F