From patchwork Mon Jun 11 06:31:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 164089 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 57194B7020 for ; Mon, 11 Jun 2012 17:33:43 +1000 (EST) Received: from localhost ([::1]:54850 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SdyCL-0003Lm-0Q for incoming@patchwork.ozlabs.org; Mon, 11 Jun 2012 02:33:57 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SdyBy-0002oj-61 for qemu-devel@nongnu.org; Mon, 11 Jun 2012 02:33:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SdyBu-0006mJ-U2 for qemu-devel@nongnu.org; Mon, 11 Jun 2012 02:33:33 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:36626) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SdyBu-0006cn-MN for qemu-devel@nongnu.org; Mon, 11 Jun 2012 02:33:30 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so5682019pbb.4 for ; Sun, 10 Jun 2012 23:33:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=VeKYHNqWRWJ90Zy8q95KCGW3gJXTZGSJ8Hx9y+ZimAY=; b=xCMHv3qghIE4QQDrhSMsRo/4fOAXXkAnAgsqJjSZE47KTjzGEqVqavdOBPolOiMcb2 k4oYLP+PTK+Z88DQ0XyvEUhgprSjiNcezNIuyY9t7gLrt4M7T/tRX/UJtknzyHTRVBRk zEyBlvjZA4o3Y5FbPkoaCLWIIvfK1S0A9biNmgu9B+ZEh/Lzr/X7IK8xrfGR2qNq8c2k qSLdWxerCGlAmU9F0jc+shawUGDfy1SMrFtQEb+Apglx+DtELlJe0x+jHxz6D9oymzMI Vv4oXJTVEhD6evc1e8dGZDvNpvLS/bj4mBsnR5MLcKsuiFNHTg+DgOfDUh2A9hnbbVzq nayA== Received: by 10.68.136.106 with SMTP id pz10mr23101228pbb.143.1339396409674; Sun, 10 Jun 2012 23:33:29 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id he9sm10703334pbc.68.2012.06.10.23.33.26 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 10 Jun 2012 23:33:28 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Mon, 11 Jun 2012 14:31:57 +0800 Message-Id: <1339396324-21368-10-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1339396324-21368-1-git-send-email-proljc@gmail.com> References: <1339396324-21368-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Subject: [Qemu-devel] [PATCH v4 09/16] target-or32: Add PIC support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add OpenRISC Programmable Interrupt Controller. Signed-off-by: Jia Liu --- hw/openrisc_pic.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c index 0d14bbe..76bd792 100644 --- a/hw/openrisc_pic.c +++ b/hw/openrisc_pic.c @@ -28,3 +28,51 @@ void cpu_openrisc_pic_reset(CPUOpenRISCState *env) env->picmr = 0x00000000; env->picsr = 0x00000000; } + +/* OpenRISC pic handler */ +static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) +{ + CPUOpenRISCState *env = (CPUOpenRISCState *)opaque; + int i; + uint32_t irq_bit = 1 << irq; + + if (irq > 31 || irq < 0) { + return; + } + + if (level) { + env->picsr |= irq_bit; + } else { + env->picsr &= ~irq_bit; + } + + for (i = 0; i < 32; i++) { + if ((env->picsr && (1 << i)) && (env->picmr && (1 << i))) { + cpu_interrupt(env, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + env->picsr &= ~(1 << i); + } + } +} + +void cpu_openrisc_pic_init(CPUOpenRISCState *env) +{ + int i; + qemu_irq *qi; + qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, env, NR_IRQS); + + for (i = 0; i < NR_IRQS; i++) { + env->irq[i] = qi[i]; + } +} + +void cpu_openrisc_store_picmr(CPUOpenRISCState *env, uint32_t value) +{ + env->picmr |= value; +} + +void cpu_openrisc_store_picsr(CPUOpenRISCState *env, uint32_t value) +{ + env->picsr &= ~value; +}