Patchwork [v4,06/16] target-or32: Add int instruction helpers

diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs
index 382190a..4286462 100644
--- a/target-openrisc/Makefile.objs
+++ b/target-openrisc/Makefile.objs
@@ -1,3 +1,3 @@ 
 obj-$(CONFIG_SOFTMMU) += machine.o
 obj-y += cpu.o excp.o intrpt.o mmu.o translate.o
-obj-y += excp_helper.o intrpt_helper.o mmu_helper.o
+obj-y += excp_helper.o int_helper.o intrpt_helper.o mmu_helper.o
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
index 4e2a49f..df354a5 100644
--- a/target-openrisc/helper.h
+++ b/target-openrisc/helper.h
@@ -22,6 +22,14 @@ 
 /* exception */
 DEF_HELPER_FLAGS_2(exception, 0, void, env, i32)
 
+/* int */
+DEF_HELPER_FLAGS_1(ff1, 0, tl, tl)
+DEF_HELPER_FLAGS_1(fl1, 0, tl, tl)
+DEF_HELPER_FLAGS_3(add, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(addc, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(sub, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(mul, 0, tl, env, tl, tl)
+
 /* interrupt */
 DEF_HELPER_FLAGS_1(rfe, 0, void, env)
 
diff --git a/target-openrisc/int_helper.c b/target-openrisc/int_helper.c
new file mode 100644
index 0000000..20f8639
--- /dev/null
+++ b/target-openrisc/int_helper.c
@@ -0,0 +1,155 @@ 
+/*
+ *  OpenRISC int helper routines
+ *
+ *  Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ *                          Feng Gao <gf91597@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "helper.h"
+#include "excp.h"
+
+target_ulong HELPER(ff1)(target_ulong x)
+{
+    target_ulong n = 0;
+
+    if (x == 0) {
+        return 0;
+    }
+
+    for (n = 32; x; n--) {
+        x <<= 1;
+    }
+    return n+1;
+}
+
+target_ulong HELPER(fl1)(target_ulong x)
+{
+    target_ulong n = 0;
+
+    if (x == 0) {
+        return 0;
+    }
+
+    for (n = 0; x; n++) {
+        x >>= 1;
+    }
+    return n;
+}
+
+target_ulong HELPER(add)(CPUOpenRISCState * env, target_ulong a, target_ulong b)
+{
+    target_ulong result;
+    result = a + b;
+
+    if (result < a) {
+        env->sr |= SR_CY;
+    } else {
+        env->sr &= ~SR_CY;
+    }
+
+    if ((a ^ b ^ -1) & (a ^ result)) {
+        env->sr |= SR_OV;
+        if (env->sr & SR_OVE) {
+            raise_exception(env, EXCP_RANGE);
+        }
+    } else {
+        env->sr &= ~SR_OV;
+    }
+    return result;
+}
+
+target_ulong HELPER(addc)(CPUOpenRISCState * env,
+                          target_ulong a, target_ulong b)
+{
+    target_ulong result;
+    int cf = env->sr & SR_CY;
+
+    if (!cf) {
+        result = a + b;
+        cf = result < a;
+    } else {
+        result = a + b + 1;
+        cf = result <= a;
+    }
+
+    if (cf) {
+        env->sr |= SR_CY;
+    } else {
+        env->sr &= ~SR_CY;
+    }
+
+    if ((a ^ b ^ -1) & (a ^ result)) {
+        env->sr |= SR_OV;
+        if (env->sr & SR_OVE) {
+            raise_exception(env, EXCP_RANGE);
+        }
+    } else {
+        env->sr &= ~SR_OV;
+    }
+    return result;
+}
+
+target_ulong HELPER(sub)(CPUOpenRISCState * env, target_ulong a, target_ulong b)
+{
+    target_ulong result;
+    result = a - b;
+    if (a >= b) {
+        env->sr |= SR_CY;
+    } else {
+        env->sr &= ~SR_CY;
+    }
+
+    if ((a ^ b) & (a ^ result)) {
+        env->sr |= SR_OV;
+        if (env->sr & SR_OVE) {
+            raise_exception(env, EXCP_RANGE);
+        }
+    } else {
+        env->sr &= ~SR_OV;
+    }
+    return result;
+}
+
+target_ulong HELPER(mul)(CPUOpenRISCState * env, target_ulong a, target_ulong b)
+{
+    uint64_t result;
+    result = a * b;
+    target_ulong high;
+
+    high = result >> TARGET_LONG_BITS;
+
+    if (((result >> (TARGET_LONG_BITS - 1)) & 0x1) == 0) {
+        if (high == 0) {
+            return result;
+        }
+    }
+
+    if (((result >> (TARGET_LONG_BITS - 1)) & 0x1) == 1) {
+        if (high == 0xffffffff) {
+            return result;
+        }
+    }
+
+    env->sr |= SR_OV;
+    env->sr |= SR_CY;
+
+    if (env->sr & SR_OVE) {
+        raise_exception(env, EXCP_RANGE);
+    }
+
+    return result;
+}