From patchwork Sat Jun 9 12:12:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 163918 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2FE78B6FBE for ; Sat, 9 Jun 2012 22:33:45 +1000 (EST) Received: from localhost ([::1]:55142 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SdKY6-0001sR-RJ for incoming@patchwork.ozlabs.org; Sat, 09 Jun 2012 08:13:46 -0400 Received: from eggs.gnu.org ([208.118.235.92]:36536) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SdKXG-0007qV-5e for qemu-devel@nongnu.org; Sat, 09 Jun 2012 08:12:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SdKXD-0002u2-V4 for qemu-devel@nongnu.org; Sat, 09 Jun 2012 08:12:53 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:36917) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SdKXD-0002sa-LZ for qemu-devel@nongnu.org; Sat, 09 Jun 2012 08:12:51 -0400 Received: by mail-ey0-f173.google.com with SMTP id k12so1735906eaa.4 for ; Sat, 09 Jun 2012 05:12:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references; bh=hUNShaQuLqRrUvxlD2jRZHJOR3jF11P6rTn4Q/yUZw4=; b=FLDMpfUze6UqEt58rZn1LU9Xt/3BiMzFpybdpFlJ81fmcx9pr2JspQToNYXYoR6LF9 jq60QS4mluE2noEpUFbv/Yb78YlJQGKZO2nliU6rn/ccbqO+3arPkqUXvqq8HmAZ9BJd T/HEqKGDAjJiXYe4X4RPkYA6jmZhqy8Rjy6j8H5mVHmbDzHqSfRtnpsD7hOVdTG5KVpC ABg+YQiVvwOeqFnujemEC6SpIsECvUIAvMrlwvzL8VGafVMpaa02iX0S8KDFL/Iz8NPg Cvonk+qxUoZ93+TcYvoxBhx4Q5TBN9xFEwCn9zd3xa4fg/hyy7Gsfrv6vgt8sxiKZpEM 16Bw== Received: by 10.14.95.72 with SMTP id o48mr4577630eef.230.1339243970590; Sat, 09 Jun 2012 05:12:50 -0700 (PDT) Received: from localhost.localdomain (blueswirl.broker.freenet6.net. [2001:5c0:1400:b::d5a3]) by mx.google.com with ESMTPS id c51sm31917591eei.12.2012.06.09.05.12.49 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 09 Jun 2012 05:12:49 -0700 (PDT) From: Blue Swirl To: qemu-devel@nongnu.org Date: Sat, 9 Jun 2012 12:12:43 +0000 Message-Id: X-Mailer: git-send-email 1.7.2.5 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.215.173 Subject: [Qemu-devel] [PATCH 4/6] qemu-log: use LOG_UNIMP for some target CPU cases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use LOG_UNIMP for some target CPU cases. Signed-off-by: Blue Swirl Acked-by: Alexander Graf --- target-i386/op_helper.c | 1 + target-microblaze/translate.c | 11 ++++-- target-ppc/helper.c | 2 +- target-s390x/translate.c | 2 +- target-sparc/ldst_helper.c | 80 ++++++++++++++++++++++++---------------- 5 files changed, 58 insertions(+), 38 deletions(-) diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index bc3b94e..2862ea4 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -3146,6 +3146,7 @@ void helper_rdpmc(void) helper_svm_check_intercept_param(SVM_EXIT_RDPMC, 0); /* currently unimplemented */ + qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n"); raise_exception_err(EXCP06_ILLOP, 0); } diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index c0a6bfd..7470149 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1539,8 +1539,10 @@ static void dec_fpu(DisasContext *dc) cpu_R[dc->ra], cpu_R[dc->rb]); break; default: - qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n", - fpu_insn, dc->pc, dc->opcode); + qemu_log_mask(LOG_UNIMP, + "unimplemented fcmp fpu_insn=%x pc=%x" + " opc=%x\n", + fpu_insn, dc->pc, dc->opcode); dc->abort_at_next_insn = 1; break; } @@ -1568,8 +1570,9 @@ static void dec_fpu(DisasContext *dc) break; default: - qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n", - fpu_insn, dc->pc, dc->opcode); + qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" + " opc=%x\n", + fpu_insn, dc->pc, dc->opcode); dc->abort_at_next_insn = 1; break; } diff --git a/target-ppc/helper.c b/target-ppc/helper.c index f556f85..3f7d8a4 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -1621,7 +1621,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) break; #endif default: - cpu_fprintf(f, "%s: unimplemented\n", __func__); + qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__); } } diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 9bf8c38..1c1baf5 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5098,7 +5098,7 @@ static void disas_s390_insn(DisasContext *s) disas_ed(s, op, r1, x2, b2, d2, r1b); break; default: - LOG_DISAS("unimplemented opcode 0x%x\n", opc); + qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%x\n", opc); gen_illegal_opcode(s, ilc); break; } diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index efe5e70..9bec7a9 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -464,16 +464,18 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, if (size == 8) { ret = env->mxccregs[3]; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00a04: /* MXCC control register */ if (size == 4) { ret = env->mxccregs[3]; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00c00: /* Module reset register */ @@ -481,21 +483,24 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, ret = env->mxccregs[5]; /* should we do something here? */ } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00f00: /* MBus port address register */ if (size == 8) { ret = env->mxccregs[7]; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; default: - DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented address, size: %d\n", addr, + size); break; } DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " @@ -719,40 +724,45 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, if (size == 8) { env->mxccdata[0] = val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00008: /* MXCC stream data register 1 */ if (size == 8) { env->mxccdata[1] = val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00010: /* MXCC stream data register 2 */ if (size == 8) { env->mxccdata[2] = val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00018: /* MXCC stream data register 3 */ if (size == 8) { env->mxccdata[3] = val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00100: /* MXCC stream source */ if (size == 8) { env->mxccregs[0] = val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); @@ -767,8 +777,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, if (size == 8) { env->mxccregs[1] = val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); @@ -783,8 +794,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, if (size == 8) { env->mxccregs[3] = val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00a04: /* MXCC control register */ @@ -792,8 +804,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) | val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00e00: /* MXCC error register */ @@ -801,21 +814,24 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, if (size == 8) { env->mxccregs[6] &= ~val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; case 0x01c00f00: /* MBus port address register */ if (size == 8) { env->mxccregs[7] = val; } else { - DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented access size: %d\n", addr, + size); } break; default: - DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, - size); + qemu_log_mask(LOG_UNIMP, + "%08x: unimplemented address, size: %d\n", addr, + size); break; } DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",