From patchwork Fri Jun 8 01:04:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 163705 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id ACACAB70C5 for ; Fri, 8 Jun 2012 14:15:01 +1000 (EST) Received: from localhost ([::1]:49097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ScqOD-0001AK-2R for incoming@patchwork.ozlabs.org; Fri, 08 Jun 2012 00:01:33 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56018) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Scncx-0007WM-VO for qemu-devel@nongnu.org; Thu, 07 Jun 2012 21:04:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Scnct-00064Q-Tz for qemu-devel@nongnu.org; Thu, 07 Jun 2012 21:04:35 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:46251) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Scnct-00063b-O6 for qemu-devel@nongnu.org; Thu, 07 Jun 2012 21:04:31 -0400 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1Scncn-0002lm-U6 from Maciej_Rozycki@mentor.com ; Thu, 07 Jun 2012 18:04:25 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 7 Jun 2012 18:03:54 -0700 Received: from [172.30.1.189] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Fri, 8 Jun 2012 02:04:23 +0100 Date: Fri, 8 Jun 2012 02:04:14 +0100 From: "Maciej W. Rozycki" To: Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 X-OriginalArrivalTime: 08 Jun 2012 01:03:54.0572 (UTC) FILETIME=[933F00C0:01CD4512] X-detected-operating-system: by eggs.gnu.org: Solaris 10 (beta) X-Received-From: 192.94.38.131 X-Mailman-Approved-At: Fri, 08 Jun 2012 00:00:47 -0400 Cc: "Maciej W. Rozycki" , Aurelien Jarno Subject: [Qemu-devel] [PATCH] MIPS: Correct FCR0 initialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Nathan Froyd This change addresses a problem where QEMU incorrectly traps on floating-point MADD group instructions with SIGILL, at least while emulating MIPS32r2 processors. These instructions use the COP1X major opcode and include ones like: madd.d $f2,$f4,$f2,$f6 Here's Nathan's original analysis of the problem: "QEMU essentially does: d = find_cpu (cpu_string) // get CPU definition fpu_init (env, d) // initialize fpu state (init FCR0, basically) cpu_reset (env) ...and the cpu_reset call clears all interesting state that fpu_init setup, then proceeds to reinitialize all the CP0 registers...but not FCR0." I have verified this change with system emulation running the GDB test suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated), there were 55 progressions and no regressions. Signed-off-by: Maciej W. Rozycki Reviewed-by: Richard Henderson --- Sent on behalf of Nathan, who's since left the company. Please apply. Maciej qemu-mips-fcr0.diff Index: qemu-git-trunk/target-mips/translate.c =================================================================== --- qemu-git-trunk.orig/target-mips/translate.c 2012-06-04 05:35:53.245610241 +0100 +++ qemu-git-trunk/target-mips/translate.c 2012-06-04 05:39:26.245563823 +0100 @@ -12776,6 +12776,7 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; + env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; env->insn_flags = env->cpu_model->insn_flags; #if defined(CONFIG_USER_ONLY)