diff mbox

MIPS: Correct FCR0 initialization

Message ID alpine.DEB.1.10.1206040722200.23962@tp.orcam.me.uk
State New
Headers show

Commit Message

Maciej W. Rozycki June 8, 2012, 1:04 a.m. UTC 
From: Nathan Froyd <froydnj@codesourcery.com>

 This change addresses a problem where QEMU incorrectly traps on 
floating-point MADD group instructions with SIGILL, at least while 
emulating MIPS32r2 processors.  These instructions use the COP1X major 
opcode and include ones like:

	madd.d	$f2,$f4,$f2,$f6

 Here's Nathan's original analysis of the problem:

"QEMU essentially does:

  d = find_cpu (cpu_string)	// get CPU definition
  fpu_init (env, d)		// initialize fpu state (init FCR0, basically)
  cpu_reset (env)

...and the cpu_reset call clears all interesting state that fpu_init
setup, then proceeds to reinitialize all the CP0 registers...but not
FCR0."

 I have verified this change with system emulation running the GDB test 
suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated), 
there were 55 progressions and no regressions.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---

 Sent on behalf of Nathan, who's since left the company.  Please apply.

  Maciej

qemu-mips-fcr0.diff

Comments

Richard Henderson June 12, 2012, 2:14 p.m. UTC | #1 
On 2012-06-07 18:04, Maciej W. Rozycki wrote:
>  I have verified this change with system emulation running the GDB test 
> suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated), 
> there were 55 progressions and no regressions.
> 
> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
> ---
> 
>  Sent on behalf of Nathan, who's since left the company.  Please apply.
> 
>   Maciej
> 
> qemu-mips-fcr0.diff
> Index: qemu-git-trunk/target-mips/translate.c
> ===================================================================
> --- qemu-git-trunk.orig/target-mips/translate.c	2012-06-04 05:35:53.245610241 +0100
> +++ qemu-git-trunk/target-mips/translate.c	2012-06-04 05:39:26.245563823 +0100
> @@ -12776,6 +12776,7 @@ void cpu_state_reset(CPUMIPSState *env)
>      env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
>      env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
>      env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
> +    env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
diff mbox

Patch

Index: qemu-git-trunk/target-mips/translate.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate.c	2012-06-04 05:35:53.245610241 +0100
+++ qemu-git-trunk/target-mips/translate.c	2012-06-04 05:39:26.245563823 +0100
@@ -12776,6 +12776,7 @@  void cpu_state_reset(CPUMIPSState *env)
     env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
     env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
     env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
+    env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
     env->insn_flags = env->cpu_model->insn_flags;
 
 #if defined(CONFIG_USER_ONLY)