@@ -395,6 +395,7 @@ obj-xtensa-y += core-fsf.o
obj-openrisc-y += openrisc_pic.o
obj-openrisc-y += openrisc_timer.o
+obj-openrisc-y += openrisc_sim.o
main.o: QEMU_CFLAGS+=$(GPROF_CFLAGS)
new file mode 100644
@@ -0,0 +1,145 @@
+/*
+ * OpenRISC simulator for use as an ISS.
+ *
+ * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ * Feng Gao <gf91597@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw.h"
+#include "openrisc_cpudev.h"
+#include "boards.h"
+#include "elf.h"
+#include "pc.h"
+#include "loader.h"
+#include "exec-memory.h"
+#include "sysemu.h"
+#include "isa.h"
+#include "qtest.h"
+
+#define KERNEL_LOAD_ADDR 0x100
+
+static struct _loaderparams {
+ uint64_t ram_size;
+ const char *kernel_filename;
+ const char *kernel_cmdline;
+ const char *initrd_filename;
+} loaderparams;
+
+static void main_cpu_reset(void *opaque)
+{
+ CPUOpenRISCState *env = opaque;
+ cpu_reset(ENV_GET_CPU(env));
+}
+
+static uint64_t openrisc_load_kernel(void)
+{
+ long kernel_size;
+ uint64_t elf_entry;
+ target_phys_addr_t entry;
+
+ if (loaderparams.kernel_filename && !qtest_enabled()) {
+ kernel_size = load_elf(loaderparams.kernel_filename, NULL, NULL,
+ &elf_entry, NULL, NULL, 1, ELF_MACHINE, 1);
+ entry = elf_entry;
+ if (kernel_size < 0) {
+ kernel_size = load_uimage(loaderparams.kernel_filename,
+ &entry, NULL, NULL);
+ }
+ if (kernel_size < 0) {
+ kernel_size = load_image_targphys(loaderparams.kernel_filename,
+ KERNEL_LOAD_ADDR,
+ ram_size - KERNEL_LOAD_ADDR);
+ entry = KERNEL_LOAD_ADDR;
+ }
+ if (kernel_size < 0) {
+ fprintf(stderr, "qemu: could not load kernel '%s'\n",
+ loaderparams.kernel_filename);
+ exit(1);
+ }
+
+ if (kernel_size > 0) {
+ return elf_entry;
+ }
+ } else {
+ entry = 0;
+ }
+
+ return entry;
+}
+
+static void openrisc_sim_init(ram_addr_t ram_size,
+ const char *boot_device,
+ const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename,
+ const char *cpu_model)
+{
+ CPUOpenRISCState *env;
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ qemu_irq *i8259;
+ ISABus *isa_bus;
+
+ if (!cpu_model) {
+ cpu_model = "or1200";
+ }
+ env = cpu_init(cpu_model);
+ if (!env) {
+ fprintf(stderr, "Unable to find CPU definition!\n");
+ exit(1);
+ }
+
+ qemu_register_reset(main_cpu_reset, env);
+ main_cpu_reset(env);
+
+ memory_region_init_ram(ram, "openrisc.ram", ram_size);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ if (kernel_filename) {
+ loaderparams.ram_size = ram_size;
+ loaderparams.kernel_filename = kernel_filename;
+ loaderparams.kernel_cmdline = kernel_cmdline;
+ env->pc = openrisc_load_kernel();
+ }
+
+ cpu_openrisc_pic_init(env);
+ cpu_openrisc_clock_init(env);
+
+ isa_bus = isa_bus_new(NULL, get_system_io());
+ i8259 = i8259_init(isa_bus, env->irq[3]);
+ isa_bus_irqs(isa_bus, i8259);
+
+ serial_mm_init(get_system_memory(), 0x90000000, 0,
+ env->irq[2], 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
+
+ if (nd_table[0].vlan) {
+ isa_ne2000_init(isa_bus, 0x92000000, 4, &nd_table[0]);
+ }
+}
+
+static QEMUMachine openrisc_sim_machine = {
+ .name = "or32-sim",
+ .desc = "or32 simulation",
+ .init = openrisc_sim_init,
+ .max_cpus = 1,
+ .is_default = 1,
+};
+
+static void openrisc_sim_machine_init(void)
+{
+ qemu_register_machine(&openrisc_sim_machine);
+}
+
+machine_init(openrisc_sim_machine_init);
Add a OpenRISC ISS dummy board. Signed-off-by: Jia Liu <proljc@gmail.com> --- Makefile.target | 1 + hw/openrisc_sim.c | 145 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 146 insertions(+) create mode 100644 hw/openrisc_sim.c