From patchwork Wed Jun 6 12:27:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 163351 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 11DCAB6EF3 for ; Wed, 6 Jun 2012 22:29:39 +1000 (EST) Received: from localhost ([::1]:56547 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ScFMm-0007bQ-TF for incoming@patchwork.ozlabs.org; Wed, 06 Jun 2012 08:29:36 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45758) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ScFMP-0007Fq-Sc for qemu-devel@nongnu.org; Wed, 06 Jun 2012 08:29:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ScFMG-0006iL-5E for qemu-devel@nongnu.org; Wed, 06 Jun 2012 08:29:13 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:38710) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ScFMF-0006I0-TI for qemu-devel@nongnu.org; Wed, 06 Jun 2012 08:29:04 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so9665647pbb.4 for ; Wed, 06 Jun 2012 05:29:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=HmW0OA56nXxnEukO1Elq2nS2Jf39Q8jE3rTY5dfm2RU=; b=e9VV/LpVtEUW3dS26gbGPit58tqKkV6xWaDxJZmLuBDpG7lp77yu4Z+a5REO3FZC7m BaD8juM789U2zvuUEKUpIfsSlS41haiqCdG19FChqNsLcIPbO3wl+771nL2mjgIaA+80 LT76GvAW7dKcpgVejpE7ZZHmlGQKGPMWoo0W7o5lT7FhY3BKsRUMjROf6m4V1Rde41rz 9mtqRnTOXIk2l+6a9WHRph4dYaEtdY9HsmneFSZwhBvJCK/zhccoEeGMDEiUiYKBxNAV 7KAHZiOBLjSGtPGn/29HRrcMrq3Dt5NZyx28v0SoJUehcW/c1pGPkZqiAlBSlFUPEfy8 P9wA== Received: by 10.68.195.102 with SMTP id id6mr8947862pbc.120.1338985742902; Wed, 06 Jun 2012 05:29:02 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id pg3sm276235pbc.2.2012.06.06.05.28.59 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 06 Jun 2012 05:29:01 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Wed, 6 Jun 2012 20:27:09 +0800 Message-Id: <1338985632-29597-14-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1338985632-29597-1-git-send-email-proljc@gmail.com> References: <1338985632-29597-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Subject: [Qemu-devel] [PATCH v3 13/16] target-or32: Add gdb stub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add gdb stub for OpenRISC. Signed-off-by: Jia Liu --- gdbstub.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 6a77a66..28c5220 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1155,6 +1155,68 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n) return sizeof(target_ulong); } +#elif defined(TARGET_OPENRISC) + +#define NUM_CORE_REGS (32 + 3) + +static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + GET_REG32(env->gpr[n]); + } else { + switch (n) { + case 32: /* PPC */ + GET_REG32(env->ppc); + break; + + case 33: /* NPC */ + GET_REG32(env->npc); + break; + + case 34: /* SR */ + GET_REG32(env->sr); + break; + + default: + break; + } + } + return 0; +} + +static int cpu_gdb_write_register(CPUOpenRISCState *env, + uint8_t *mem_buf, int n) +{ + uint32_t tmp; + + if (n > NUM_CORE_REGS) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->gpr[n] = tmp; + } else { + switch (n) { + case 32: /* PPC */ + env->ppc = tmp; + break; + + case 33: /* NPC */ + env->npc = tmp; + break; + + case 34: /* SR */ + env->sr = tmp; + break; + + default: + break; + } + } + return 4; +} #elif defined (TARGET_SH4) /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ @@ -1924,6 +1986,8 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) } #elif defined (TARGET_MICROBLAZE) s->c_cpu->sregs[SR_PC] = pc; +#elif defined(TARGET_OPENRISC) + s->c_cpu->pc = pc; #elif defined (TARGET_CRIS) s->c_cpu->pc = pc; #elif defined (TARGET_ALPHA)