Patchwork [4/4] ARM i.MX5: Add nand oftree support

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Submitter Sascha Hauer
Date June 6, 2012, 10:33 a.m.
Message ID <1338978796-26129-5-git-send-email-s.hauer@pengutronix.de>
Download mbox | patch
Permalink /patch/163314/
State Not Applicable
Headers show

Comments

Sascha Hauer - June 6, 2012, 10:33 a.m.
This adds snippets to the i.MX51/53 devicetrees for the nand
flash controller.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boot/dts/imx51.dtsi        |    7 +++++++
 arch/arm/boot/dts/imx53.dtsi        |    7 +++++++
 arch/arm/mach-imx/clk-imx51-imx53.c |    2 ++
 3 files changed, 16 insertions(+)
Shawn Guo - June 7, 2012, 2:29 a.m.
On Wed, Jun 06, 2012 at 12:33:16PM +0200, Sascha Hauer wrote:
> This adds snippets to the i.MX51/53 devicetrees for the nand
> flash controller.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Sascha Hauer - June 7, 2012, 9:43 a.m.
On Thu, Jun 07, 2012 at 10:29:54AM +0800, Shawn Guo wrote:
> On Wed, Jun 06, 2012 at 12:33:16PM +0200, Sascha Hauer wrote:
> > This adds snippets to the i.MX51/53 devicetrees for the nand
> > flash controller.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> 
> Acked-by: Shawn Guo <shawn.guo@linaro.org>

Thanks. Will address Artems comments and resend.

Sascha

Patch

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index bfa65ab..39eb88e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -259,6 +259,13 @@ 
 				status = "disabled";
 			};
 
+			nand@83fdb000 {
+				compatible = "fsl,imx51-nand";
+				reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
 			ssi3: ssi@83fe8000 {
 				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 				reg = <0x83fe8000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index e3e8694..2b5caf9 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -314,6 +314,13 @@ 
 				status = "disabled";
 			};
 
+			nand@63fdb000 {
+				compatible = "fsl,imx53-nand";
+				reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
 			ssi3: ssi@63fe8000 {
 				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 				reg = <0x63fe8000 0x4000>;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index fcd94f3..7b525c1 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -357,6 +357,7 @@  int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
 	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
+	clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
 
 	/* set the usboh3 parent to pll2_sw */
 	clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -446,6 +447,7 @@  int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
 	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+	clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
 
 	/* set SDHC root clock to 200MHZ*/
 	clk_set_rate(clk[esdhc_a_podf], 200000000);