From patchwork Tue Jun 5 01:21:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 162935 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8FC29B6FFF for ; Tue, 5 Jun 2012 12:33:34 +1000 (EST) Received: from localhost ([::1]:34530 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SbiVR-0003Tx-2B for incoming@patchwork.ozlabs.org; Mon, 04 Jun 2012 21:24:21 -0400 Received: from eggs.gnu.org ([208.118.235.92]:35972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SbiUk-0001oC-3y for qemu-devel@nongnu.org; Mon, 04 Jun 2012 21:23:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SbiUg-00084n-A6 for qemu-devel@nongnu.org; Mon, 04 Jun 2012 21:23:37 -0400 Received: from cantor2.suse.de ([195.135.220.15]:52655 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SbiUg-00084U-0G for qemu-devel@nongnu.org; Mon, 04 Jun 2012 21:23:34 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id E28FE919A3; Tue, 5 Jun 2012 03:23:32 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Tue, 5 Jun 2012 03:21:35 +0200 Message-Id: <1338859366-20689-4-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1338859366-20689-1-git-send-email-afaerber@suse.de> References: <1338859366-20689-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH 03/74] omap: Use cpu_arm_init() to store ARMCPU in omap_mpu_state_s X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix tab indentations of comments, add braces, use cpu_reset(). Signed-off-by: Andreas Färber Acked-by: Peter Maydell --- hw/nseries.c | 6 +++--- hw/omap.h | 2 +- hw/omap1.c | 20 +++++++++++--------- hw/omap2.c | 8 ++++---- hw/omap_sx1.c | 2 +- hw/palm.c | 2 +- 6 files changed, 21 insertions(+), 19 deletions(-) diff --git a/hw/nseries.c b/hw/nseries.c index a5cfa8c..b8c6a29 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -1023,7 +1023,7 @@ static void n8x0_boot_init(void *opaque) n800_dss_init(&s->blizzard); /* CPU setup */ - s->cpu->env->GE = 0x5; + s->cpu->cpu->env.GE = 0x5; /* If the machine has a slided keyboard, open it */ if (s->kbd) @@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device, binfo->kernel_filename = kernel_filename; binfo->kernel_cmdline = kernel_cmdline; binfo->initrd_filename = initrd_filename; - arm_load_kernel(s->cpu->env, binfo); + arm_load_kernel(&s->cpu->cpu->env, binfo); qemu_register_reset(n8x0_boot_init, s); } @@ -1338,7 +1338,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device, int rom_size; uint8_t nolo_tags[0x10000]; /* No, wait, better start at the ROM. */ - s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000; + s->cpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; /* This is intended for loading the `secondary.bin' program from * Nokia images (the NOLO bootloader). The entry point seems diff --git a/hw/omap.h b/hw/omap.h index 6c3d004..2819e5d 100644 --- a/hw/omap.h +++ b/hw/omap.h @@ -804,7 +804,7 @@ struct omap_mpu_state_s { omap3630, } mpu_model; - CPUARMState *env; + ARMCPU *cpu; qemu_irq *drq; diff --git a/hw/omap1.c b/hw/omap1.c index 80d47f0..a997d30 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -1519,8 +1519,9 @@ static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, { omap_clk clk; - if (value & (1 << 11)) /* SETARM_IDLE */ - cpu_interrupt(s->env, CPU_INTERRUPT_HALT); + if (value & (1 << 11)) { /* SETARM_IDLE */ + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT); + } if (!(value & (1 << 10))) /* WKUP_MODE */ qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ @@ -1734,7 +1735,7 @@ static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr, case 0x18: /* DSP_SYSST */ return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | - (s->env->halted << 6); /* Quite useless... */ + (s->cpu->env.halted << 6); /* Quite useless... */ } OMAP_BAD_REG(addr); @@ -3701,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque) omap_lpg_reset(mpu->led[0]); omap_lpg_reset(mpu->led[1]); omap_clkm_reset(mpu); - cpu_state_reset(mpu->env); + cpu_reset(CPU(mpu->cpu)); } static const struct omap_map_s { @@ -3751,8 +3752,9 @@ void omap_mpu_wakeup(void *opaque, int irq, int req) { struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; - if (mpu->env->halted) - cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); + if (mpu->cpu->env.halted) { + cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB); + } } static const struct dma_irq_map omap1_dma_irq_map[] = { @@ -3829,8 +3831,8 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, /* Core */ s->mpu_model = omap310; - s->env = cpu_init(core); - if (!s->env) { + s->cpu = cpu_arm_init(core); + if (s->cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } @@ -3852,7 +3854,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); - cpu_irq = arm_pic_init_cpu(s->env); + cpu_irq = arm_pic_init_cpu(&s->cpu->env); s->ih[0] = qdev_create(NULL, "omap-intc"); qdev_prop_set_uint32(s->ih[0], "size", 0x100); qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); diff --git a/hw/omap2.c b/hw/omap2.c index 42fce5e..196c4b6 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -2222,7 +2222,7 @@ static void omap2_mpu_reset(void *opaque) omap_mmc_reset(mpu->mmc); omap_mcspi_reset(mpu->mcspi[0]); omap_mcspi_reset(mpu->mcspi[1]); - cpu_state_reset(mpu->env); + cpu_reset(CPU(mpu->cpu)); } static int omap2_validate_addr(struct omap_mpu_state_s *s, @@ -2253,8 +2253,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, /* Core */ s->mpu_model = omap2420; - s->env = cpu_init(core ?: "arm1136-r2"); - if (!s->env) { + s->cpu = cpu_arm_init(core ?: "arm1136-r2"); + if (s->cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } @@ -2277,7 +2277,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54); /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ - cpu_irq = arm_pic_init_cpu(s->env); + cpu_irq = arm_pic_init_cpu(&s->cpu->env); s->ih[0] = qdev_create(NULL, "omap2-intc"); qdev_prop_set_uint8(s->ih[0], "revision", 0x21); qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk")); diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c index 4e8ec4a..c7618c6 100644 --- a/hw/omap_sx1.c +++ b/hw/omap_sx1.c @@ -202,7 +202,7 @@ static void sx1_init(ram_addr_t ram_size, sx1_binfo.kernel_filename = kernel_filename; sx1_binfo.kernel_cmdline = kernel_cmdline; sx1_binfo.initrd_filename = initrd_filename; - arm_load_kernel(cpu->env, &sx1_binfo); + arm_load_kernel(&cpu->cpu->env, &sx1_binfo); } /* TODO: fix next line */ diff --git a/hw/palm.c b/hw/palm.c index b1252ab..6d81829 100644 --- a/hw/palm.c +++ b/hw/palm.c @@ -265,7 +265,7 @@ static void palmte_init(ram_addr_t ram_size, palmte_binfo.kernel_filename = kernel_filename; palmte_binfo.kernel_cmdline = kernel_cmdline; palmte_binfo.initrd_filename = initrd_filename; - arm_load_kernel(cpu->env, &palmte_binfo); + arm_load_kernel(&cpu->cpu->env, &palmte_binfo); } /* FIXME: We shouldn't really be doing this here. The LCD controller