Comments
Patch
@@ -156,11 +156,13 @@ extern int cris_cpu_version;
" -D__CRIS_arch_tune=" CRIS_DEFAULT_TUNE "}}}}}"\
CRIS_ARCH_CPP_DEFAULT
-/* Override previous definitions (linux.h). */
+/* Override previous definitions (../linux.h). */
#undef CC1_SPEC
#define CC1_SPEC \
"%{metrax4:-march=v3}\
%{metrax100:-march=v8}\
+ %{march=*:-march=%*}\
+ %{mcpu=*:-mcpu=%*}\
%(cc1_subtarget)"
/* For the cris-*-elf subtarget. */
@@ -190,7 +192,9 @@ extern int cris_cpu_version;
MAYBE_AS_NO_MUL_BUG_ABORT \
"%(asm_subtarget)\
%{march=*:%{mcpu=*:%edo not specify both -march=... and -mcpu=...}}\
- %{march=v32:--march=v32} %{mcpu=v32:--march=v32}"
+ %{march=v0|mcpu=v0|march=v3|mcpu=v3|march=v8|mcpu=v8:--march=v0_v10}\
+ %{march=v10|mcpu=v10:--march=v10}\
+ %{march=v32|mcpu=v32:--march=v32}"
/* For the cris-*-elf subtarget. */
#define CRIS_ASM_SUBTARGET_SPEC \
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can assemble for the "other" variant, with the twist
+ that the gcc option -march=v0 isn't valid for the assembler. */
+ .text
+#if OTHER_ISA == 32
+ addoq 42,$r1,$acr
+#else
+0:
+ move.d [$r2=$r0+42],$r1
+ bwf 0b
+ nop
+#endif
@@ -0,0 +1,23 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can (generate code and) assemble for the "other"
+ variant, with the twist that the gcc option -march=v0 isn't
+ valid for the assembler. We don't check that the generated code
+ is for the other variant; other tests cover that already, but they
+ don't *assemble* the result. We can't trust the prologue and
+ epilogue to contain incompatible insns (they actually deliberately
+ don't, usually and it'd be brittle to tweak the function signature
+ to make it so), so we force some with inline asm. */
+
+void f(void)
+{
+#if OTHER_ISA == 32
+ asm volatile ("addoq 42,$r11,$acr");
+#else
+ asm volatile ("0: move.d [$r12=$sp+42],$r10\n\t"
+ "bwf 0b\n\t"
+ "nop");
+#endif
+}
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized. */
+
+#include "inasm-other.c"
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized. */
+
+#include "inasm-other.c"
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized. */
+
+#include "asm-other.S"
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized. */
+
+#include "asm-other.S"