Message ID | 1338129294-16742-3-git-send-email-jcmvbkbc@gmail.com |
---|---|
State | New |
Headers | show |
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 2094227..43a6611 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -516,6 +516,7 @@ static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb, *wi = (++env->autorefill_idx) & 0x3; split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, *wi, ei); xtensa_tlb_set_entry(env, dtlb, *wi, *ei, vpn, pte); + env->sregs[EXCVADDR] = vaddr; qemu_log("%s: autorefill(%08x): %08x -> %08x\n", __func__, vaddr, vpn, pte); }
According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, even if the miss is handled entirely by processor hardware. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> --- target-xtensa/helper.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)