From patchwork Sun May 27 02:10:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 161519 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3310BB6FA1 for ; Sun, 27 May 2012 12:15:23 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SYSwz-0008NM-G5; Sun, 27 May 2012 02:11:21 +0000 Received: from mail-out.m-online.net ([212.18.0.10]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SYSwr-0008Mv-13 for linux-arm-kernel@lists.infradead.org; Sun, 27 May 2012 02:11:18 +0000 Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3W0PnM6zwbz3hhXj; Sun, 27 May 2012 04:11:03 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.8.164]) by mail.m-online.net (Postfix) with ESMTP id 3W0PnM2DK6z4KK3l; Sun, 27 May 2012 04:11:03 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from smtp-auth.mnet-online.de ([192.168.8.180]) by localhost (dynscan1.mail.m-online.net [192.168.8.164]) (amavisd-new, port 10024) with ESMTP id mOwq14kG8+OI; Sun, 27 May 2012 04:11:02 +0200 (CEST) Received: from mashiro.lan (unknown [195.140.253.167]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA; Sun, 27 May 2012 04:11:00 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] MXS: Set I2C timing registers for mxs-i2c Date: Sun, 27 May 2012 04:10:55 +0200 Message-Id: <1338084656-11961-1-git-send-email-marex@denx.de> X-Mailer: git-send-email 1.7.10 MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.18.0.10 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Marek Vasut , Fabio Estevam , Wolfgang Denk , Detlev Zundel , Sascha Hauer , Wolfram Sang , linux-i2c@vger.kernel.org, =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Shawn Guo , Dong Aisheng , Stefano Babic X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org This patch configures the I2C bus timing registers according to information passed via DT. Currently, 100kHz and 400kHz modes are supported. Signed-off-by: Marek Vasut Cc: Detlev Zundel CC: Dong Aisheng CC: Fabio Estevam Cc: Linux ARM kernel Cc: linux-i2c@vger.kernel.org CC: Sascha Hauer CC: Shawn Guo Cc: Stefano Babic CC: Uwe Kleine-König Cc: Wolfgang Denk Cc: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-mxs.txt | 1 + arch/arm/boot/dts/imx28.dtsi | 2 + drivers/i2c/busses/i2c-mxs.c | 64 +++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt index 1bfc02d..790b5c6 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Should be "fsl,-i2c" - reg: Should contain registers location and length - interrupts: Should contain ERROR and DMA interrupts +- speed: Speed of the bus in kHz (400 or 100 are supported) Examples: diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 4634cb8..d927155 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -381,6 +381,7 @@ compatible = "fsl,imx28-i2c"; reg = <0x80058000 2000>; interrupts = <111 68>; + fsl,speed = <400>; status = "disabled"; }; @@ -390,6 +391,7 @@ compatible = "fsl,imx28-i2c"; reg = <0x8005a000 2000>; interrupts = <110 69>; + fsl,speed = <400>; status = "disabled"; }; diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c index 04eb441..fff0a09 100644 --- a/drivers/i2c/busses/i2c-mxs.c +++ b/drivers/i2c/busses/i2c-mxs.c @@ -46,6 +46,10 @@ #define MXS_I2C_CTRL0_DIRECTION 0x00010000 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF) +#define MXS_I2C_TIMING0 (0x10) +#define MXS_I2C_TIMING1 (0x20) +#define MXS_I2C_TIMING2 (0x30) + #define MXS_I2C_CTRL1 (0x40) #define MXS_I2C_CTRL1_SET (0x44) #define MXS_I2C_CTRL1_CLR (0x48) @@ -97,6 +101,24 @@ #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ MXS_I2C_CTRL0_MASTER_MODE) +struct mxs_i2c_speed_config { + uint32_t timing0; + uint32_t timing1; + uint32_t timing2; +}; + +const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = { + .timing0 = 0x00780030, + .timing1 = 0x00800030, + .timing2 = 0x0015000d, +}; + +const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = { + .timing0 = 0x000f0007, + .timing1 = 0x001f000f, + .timing2 = 0x0015000d, +}; + /** * struct mxs_i2c_dev - per device, private MXS-I2C data * @@ -112,11 +134,17 @@ struct mxs_i2c_dev { struct completion cmd_complete; u32 cmd_err; struct i2c_adapter adapter; + const struct mxs_i2c_speed_config *speed; }; static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) { stmp_reset_block(i2c->regs); + + writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0); + writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1); + writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2); + writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, i2c->regs + MXS_I2C_QUEUECTRL_SET); @@ -319,6 +347,38 @@ static const struct i2c_algorithm mxs_i2c_algo = { .functionality = mxs_i2c_func, }; +#ifdef CONFIG_OF +static int mxs_i2c_get_ofdata(struct platform_device *pdev, + struct mxs_i2c_dev *i2c) +{ + const __be32 *speed; + uint32_t speed_khz; + struct device_node *node = pdev->dev.of_node; + + if (!node) + return -EINVAL; + + i2c->speed = &mxs_i2c_95kHz_config; + speed = of_get_property(node, "fsl,speed", NULL); + if (!speed) + dev_warn(&pdev->dev, + "No I2C speed selected, using 100kHz\n"); + + speed_khz = be32_to_cpup(speed); + if (speed_khz == 400) + i2c->speed = &mxs_i2c_400kHz_config; + else if (speed_khz != 100) + dev_warn(&pdev->dev, + "Invalid I2C speed selected, using 100kHz\n"); + + return 0; +} +#else +static int mxs_i2c_get_ofdata(struct platform_device *pdev, + struct mxs_i2c_dev *i2c) +{ } +#endif /* CONFIG_OF */ + static int __devinit mxs_i2c_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -357,6 +417,10 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev) if (err) return err; + err = mxs_i2c_get_ofdata(pdev, i2c); + if (err) + return err; + i2c->dev = dev; platform_set_drvdata(pdev, i2c);