From patchwork Fri May 25 11:53:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 161311 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 890C8B6EF1 for ; Fri, 25 May 2012 21:52:05 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6006A2819E; Fri, 25 May 2012 13:52:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x3swgUv1uWIw; Fri, 25 May 2012 13:52:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 46363281A1; Fri, 25 May 2012 13:52:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9FCDE281A1 for ; Fri, 25 May 2012 13:51:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fmV9tu6svyHL for ; Fri, 25 May 2012 13:51:57 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by theia.denx.de (Postfix) with ESMTP id 754722819E for ; Fri, 25 May 2012 13:51:55 +0200 (CEST) Received: from epcpsbgm1.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M4K00IIZU9RNCP0@mailout4.samsung.com> for u-boot@lists.denx.de; Fri, 25 May 2012 20:51:53 +0900 (KST) X-AuditID: cbfee61a-b7fe76d0000023f5-37-4fbf7259496c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id F0.BC.09205.9527FBF4; Fri, 25 May 2012 20:51:53 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M4K00LCRU6DUZ50@mmp1.samsung.com> for u-boot@lists.denx.de; Fri, 25 May 2012 20:51:53 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Fri, 25 May 2012 17:23:16 +0530 Message-id: <1337946798-1660-3-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1337946798-1660-1-git-send-email-rajeshwari.s@samsung.com> References: <1337946798-1660-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCJMWRmVeSWpSXmKPExsVy+t9jAd3Iov3+BldnyFu83dvJ7sDocfbO DsYAxigum5TUnMyy1CJ9uwSujEvnv7AWPBOpuPhxAVsD4z2BLkZODgkBE4m3c36wQthiEhfu rWfrYuTiEBJYxCjRsOkFI4SzikniwK8GNpAqNgEjia0npzGC2CICEhK/+q+CFTELtDNKdG27 xAySEBawlrjR8ZEFxGYRUJVYc+UZWAOvgLvE8hX9UOsUJI5N/Qpmcwp4SNxcsowJxBYCqtny dxXrBEbeBYwMqxhFUwuSC4qT0nMN9YoTc4tL89L1kvNzNzGC/f5MagfjygaLQ4wCHIxKPLwX Yvb7C7EmlhVX5h5ilOBgVhLhZUkDCvGmJFZWpRblxxeV5qQWH2KU5mBREue1W7zDX0ggPbEk NTs1tSC1CCbLxMEp1cAYqFautX/1q2Z9/yCL8+zLV+3ZVcihc7F4d/i3HMkDTWLH1I/d2JN+ 0uLzrhmFLrO2HpkbLtZ5p+2XsY3fdqM5jevUzLdMX3l8w+ReQ2O2lXn/HqeoLNHQOvP+xRm5 NXN/GdrMszEy4OtsL2m8ryXfdmmySnPM4iUctr+uFGtffXV9iY7guuoyJZbijERDLeai4kQA /6rd8fcBAAA= X-TM-AS-MML: No Cc: patches@linaro.org, afleming@gmail.com Subject: [U-Boot] [PATCH 2/4] EXYNOS5: PINMUX: Add pinmux for SDMMC4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add pinmux support for SDMMC4 on EXYNOS5. Signed-off-by: Terry Lambert Signed-off-by: Rajeshwari Shinde --- This patch is based on: "EXYNOS5: PINMUX: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 24 +++++++++++++++++------- 1 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 103bcbb..9319fd6 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -32,7 +32,7 @@ int exynos5_pinmux_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext; - int i, start, count; + int i, start, count, pin, pin_ext, drv; switch (peripheral) { case PERIPH_ID_UART0: @@ -66,6 +66,10 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: + case PERIPH_ID_SDMMC4: + pin = GPIO_FUNC(0x2); + pin_ext = GPIO_FUNC(0x3); + drv = GPIO_DRV_4X; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1; @@ -79,6 +83,12 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC3: bank = &gpio1->c3; bank_ext = NULL; break; + case PERIPH_ID_SDMMC4: + bank = &gpio1->c0; bank_ext = &gpio1->c1; + pin = GPIO_FUNC(0x3); + pin_ext = GPIO_FUNC(0x4); + drv = GPIO_DRV_2X; + break; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bit mode", @@ -87,20 +97,20 @@ int exynos5_pinmux_config(int peripheral, int flags) } if (flags & PINMUX_FLAG_8BIT_MODE) { for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(bank_ext, i, pin_ext); s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank_ext, i, drv); } } for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank, i, drv); } for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank, i, drv); } break; case PERIPH_ID_SROMC: