From patchwork Fri May 25 11:53:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 161310 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3C3D4B6F6E for ; Fri, 25 May 2012 21:51:30 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 08CE6281B1; Fri, 25 May 2012 13:51:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TsDfMfaJBWoh; Fri, 25 May 2012 13:51:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 05FC1281A2; Fri, 25 May 2012 13:51:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C83C6281A2 for ; Fri, 25 May 2012 13:51:21 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lhabBhQIfsTa for ; Fri, 25 May 2012 13:51:20 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by theia.denx.de (Postfix) with ESMTP id C801A2819A for ; Fri, 25 May 2012 13:51:19 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M4K008B1U9EOQL0@mailout3.samsung.com> for u-boot@lists.denx.de; Fri, 25 May 2012 20:51:15 +0900 (KST) X-AuditID: cbfee61b-b7faf6d000001f49-09-4fbf723314bf Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 46.B5.08009.3327FBF4; Fri, 25 May 2012 20:51:15 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M4K00LCRU6DUZ50@mmp1.samsung.com> for u-boot@lists.denx.de; Fri, 25 May 2012 20:51:15 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Fri, 25 May 2012 17:23:15 +0530 Message-id: <1337946798-1660-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1337946798-1660-1-git-send-email-rajeshwari.s@samsung.com> References: <1337946798-1660-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMJMWRmVeSWpSXmKPExsVy+t9jAV3jov3+Bjsfclu83dvJ7sDocfbO DsYAxigum5TUnMyy1CJ9uwSujO1tHcwFl+QrXtxbwtrA+F2yi5GTQ0LARGLT/WWMELaYxIV7 69m6GLk4hAQWMUq8nPOGBSQhJLCKSWLGu3wQm03ASGLryWlgDSICEhK/+q8ygjQwC7QzSnRt u8QMkhAWsJQ4s+wXO4jNIqAq8XvlHLBBvALuEhMOHGaF2KYgcWzqVzCbU8BD4uaSZUwQy9wl tvxdxTqBkXcBI8MqRtHUguSC4qT0XCO94sTc4tK8dL3k/NxNjGCvP5PewbiqweIQowAHoxIP b2XUfn8h1sSy4srcQ4wSHMxKIrwsaUAh3pTEyqrUovz4otKc1OJDjNIcLErivE+W7PAXEkhP LEnNTk0tSC2CyTJxcEo1MPbtC1Qt/OYVIDkp6XXD+5/2fkc/havONE7vWrphrtj7zDO1XKEH X03bpvY96pfhGUkV/bjMQ7bF/D7qn8rlRP52rbgWuq1NZk7DycynRbNtZAVv/ghK0n+/59jJ Rb/zJ3m/fSB+v7JOulCY5bVEnQzPraUdu871XAgpYtt+K2HbFo6+qIktnUosxRmJhlrMRcWJ AM62qZL2AQAA X-TM-AS-MML: No Cc: patches@linaro.org, afleming@gmail.com Subject: [U-Boot] [PATCH 1/4] EXYNOS: MSHCI: Add clock for EXYNOS5 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add apis to set and get divider clock ratio for FSYS_BLK on EXYNOS5. Signed-off-by: Terry Lambert Signed-off-by: Alim Akhtar Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock.c | 96 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 4 + 2 files changed, 100 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 3b86b0c..3af1aac 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -414,6 +414,90 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +static unsigned long exynos5_get_mshci_clk_div(enum periph_id peripheral) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + u32 *addr; + unsigned int div_mmc, div_mmc_pre; + unsigned int mpll_clock, sclk_mmc; + + mpll_clock = get_pll_clk(MPLL); + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] + */ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + addr = &clk->div_fsys1; + break; + case PERIPH_ID_SDMMC2: + addr = &clk->div_fsys2; + break; + case PERIPH_ID_SDMMC4: + addr = &clk->div_fsys3; + break; + default: + debug("invalid peripheral\n"); + return -1; + } + + div_mmc = (readl(addr) & 0xf) + 1; + div_mmc_pre = ((readl(addr) & 0xff00) >> 8) + 1; + sclk_mmc = (mpll_clock / div_mmc) / div_mmc_pre; + + return sclk_mmc; +} + +static int exynos5_set_mshci_clk_div(enum periph_id peripheral) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + u32 *addr; + unsigned int clock; + unsigned int tmp; + unsigned int i; + + /* get mpll clock */ + clock = get_pll_clk(MPLL) / 1000000; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] + */ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + addr = &clk->div_fsys1; + break; + case PERIPH_ID_SDMMC2: + addr = &clk->div_fsys2; + break; + case PERIPH_ID_SDMMC4: + addr = &clk->div_fsys3; + break; + default: + debug("invalid peripheral\n"); + return -1; + } + tmp = readl(addr) & ~0xff0f; + for (i = 0; i <= 0xf; i++) { + if ((clock / (i + 1)) <= 400) { + writel(tmp | i << 0, addr); + break; + } + } + return 0; +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { @@ -651,6 +735,18 @@ void set_mmc_clk(int dev_index, unsigned int div) exynos4_set_mmc_clk(dev_index, div); } +unsigned long get_mshci_clk_div(enum periph_id peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_get_mshci_clk_div(peripheral); +} + +int set_mshci_clk_div(enum periph_id peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_set_mshci_clk_div(peripheral); +} + unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 72dc655..4a6fa90 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -22,6 +22,8 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_ +#include + #define APLL 0 #define MPLL 1 #define EPLL 2 @@ -34,6 +36,8 @@ unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); +unsigned long get_mshci_clk_div(enum periph_id peripheral); +int set_mshci_clk_div(enum periph_id peripheral); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void);