Patchwork [1/9] unicore32-softmmu: make exceptions generated in unicore32 architecture

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Submitter Guan Xuetao
Date May 25, 2012, 11:28 a.m.
Message ID <389234add14c715e5e37334419d7c493bf5f8992.1337944756.git.gxt@mprc.pku.edu.cn>
Download mbox | patch
Permalink /patch/161298/
State New
Headers show

Comments

Guan Xuetao - May 25, 2012, 11:28 a.m.
We need to specify the exception type in proper situations.
Then it could make exceptions generated correctly and timely.

Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
 cpu-exec.c             |    1 +
 linux-user/main.c      |    3 ++-
 target-unicore32/cpu.h |    6 ++++--
 3 files changed, 7 insertions(+), 3 deletions(-)

Patch

diff --git a/cpu-exec.c b/cpu-exec.c
index 0344cd5..929b535 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -416,6 +416,7 @@  int cpu_exec(CPUArchState *env)
 #elif defined(TARGET_UNICORE32)
                     if (interrupt_request & CPU_INTERRUPT_HARD
                         && !(env->uncached_asr & ASR_I)) {
+                        env->exception_index = UC32_EXCP_INTR;
                         do_interrupt(env);
                         next_tb = 0;
                     }
diff --git a/linux-user/main.c b/linux-user/main.c
index 191b750..a394409 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -958,7 +958,8 @@  void cpu_loop(CPUUniCore32State *env)
                 }
             }
             break;
-        case UC32_EXCP_TRAP:
+        case UC32_EXCP_DTRAP:
+        case UC32_EXCP_ITRAP:
             info.si_signo = SIGSEGV;
             info.si_errno = 0;
             /* XXX: check env->error_code */
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 81c14ff..66c42f5 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -89,8 +89,10 @@  typedef struct CPUUniCore32State {
 #define ASR_NZCV                (ASR_N | ASR_Z | ASR_C | ASR_V)
 #define ASR_RESERVED            (~(ASR_M | ASR_I | ASR_NZCV))
 
-#define UC32_EXCP_PRIV          (ASR_MODE_PRIV)
-#define UC32_EXCP_TRAP          (ASR_MODE_TRAP)
+#define UC32_EXCP_PRIV          (1)
+#define UC32_EXCP_ITRAP         (2)
+#define UC32_EXCP_DTRAP         (3)
+#define UC32_EXCP_INTR          (4)
 
 /* Return the current ASR value.  */
 target_ulong cpu_asr_read(CPUUniCore32State *env1);