From patchwork Wed May 23 03:08:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 160822 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7426FB6FA1 for ; Wed, 23 May 2012 14:54:37 +1000 (EST) Received: from localhost ([::1]:40285 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SX1zf-0004bl-Ps for incoming@patchwork.ozlabs.org; Tue, 22 May 2012 23:12:11 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SX1x2-0001L3-80 for qemu-devel@nongnu.org; Tue, 22 May 2012 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SX1ws-0005oD-Qa for qemu-devel@nongnu.org; Tue, 22 May 2012 23:09:27 -0400 Received: from cantor2.suse.de ([195.135.220.15]:35624 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SX1ws-0005me-2X; Tue, 22 May 2012 23:09:18 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id B510797155; Wed, 23 May 2012 05:09:16 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 23 May 2012 05:08:06 +0200 Message-Id: <1337742502-28565-44-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1337742502-28565-1-git-send-email-afaerber@suse.de> References: <1337742502-28565-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Peter Maydell , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , "open list:PowerPC" , Paul Brook , "Edgar E. Iglesias" , Guan Xuetao , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH qom-next 43/59] cpus: Pass CPUState to [qemu_]cpu_has_work() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: Andreas Färber --- cpu-all.h | 2 -- cpu-exec.c | 8 +++----- cpus.c | 2 +- hw/spapr_hcall.c | 2 +- hw/xtensa_pic.c | 2 +- include/qemu/cpu.h | 10 ++++++++++ target-alpha/cpu.c | 2 +- target-alpha/cpu.h | 4 +++- target-arm/cpu.h | 4 +++- target-cris/cpu.h | 4 +++- target-i386/cpu.h | 4 +++- target-lm32/cpu.h | 4 +++- target-m68k/cpu.h | 4 +++- target-microblaze/cpu.h | 4 +++- target-mips/cpu.h | 11 ++++++----- target-ppc/cpu.h | 4 +++- target-s390x/cpu.h | 4 +++- target-sh4/cpu.h | 4 +++- target-sparc/cpu.h | 4 +++- target-unicore32/cpu.c | 2 +- target-unicore32/cpu.h | 4 +++- target-xtensa/cpu.h | 4 +++- 22 files changed, 63 insertions(+), 30 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index af85e7d..0adfcf5 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -415,8 +415,6 @@ void cpu_reset_interrupt(CPUArchState *env, int mask); void cpu_exit(CPUArchState *s); -bool qemu_cpu_has_work(CPUArchState *env); - /* Breakpoint/watchpoint flags */ #define BP_MEM_READ 0x01 #define BP_MEM_WRITE 0x02 diff --git a/cpu-exec.c b/cpu-exec.c index 83cac93..da0c17a 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -27,9 +27,9 @@ int tb_invalidated_flag; //#define CONFIG_DEBUG_EXEC -bool qemu_cpu_has_work(CPUArchState *env) +bool qemu_cpu_has_work(CPUState *cpu) { - return cpu_has_work(env); + return cpu_has_work(cpu); } void cpu_loop_exit(CPUArchState *env) @@ -184,16 +184,14 @@ volatile sig_atomic_t exit_request; int cpu_exec(CPUArchState *env) { -#ifdef TARGET_PPC CPUState *cpu = ENV_GET_CPU(env); -#endif int ret, interrupt_request; TranslationBlock *tb; uint8_t *tc_ptr; tcg_target_ulong next_tb; if (env->halted) { - if (!cpu_has_work(env)) { + if (!cpu_has_work(cpu)) { return EXCP_HALTED; } diff --git a/cpus.c b/cpus.c index 83880e7..ba7fb1c 100644 --- a/cpus.c +++ b/cpus.c @@ -443,7 +443,7 @@ static bool cpu_thread_is_idle(CPUArchState *env) if (cpu->stopped || !runstate_is_running()) { return true; } - if (!env->halted || qemu_cpu_has_work(env) || kvm_irqchip_in_kernel()) { + if (!env->halted || qemu_cpu_has_work(cpu) || kvm_irqchip_in_kernel()) { return false; } return true; diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c index 47fca58..ebb271c 100644 --- a/hw/spapr_hcall.c +++ b/hw/spapr_hcall.c @@ -549,7 +549,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, env->msr |= (1ULL << MSR_EE); hreg_compute_hflags(env); - if (!cpu_has_work(env)) { + if (!cpu_has_work(CPU(cpu))) { env->halted = 1; } return H_SUCCESS; diff --git a/hw/xtensa_pic.c b/hw/xtensa_pic.c index 8b9c051..1ec70cd 100644 --- a/hw/xtensa_pic.c +++ b/hw/xtensa_pic.c @@ -131,7 +131,7 @@ static void xtensa_ccompare_cb(void *opaque) if (env->halted) { env->halt_clock = qemu_get_clock_ns(vm_clock); xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]); - if (!cpu_has_work(env)) { + if (!cpu_has_work(CPU(cpu))) { env->sregs[CCOUNT] = env->wake_ccount + 1; xtensa_rearm_ccompare_timer(env); } diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index eea6175..f04da6e 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -87,6 +87,16 @@ struct CPUState { void cpu_reset(CPUState *cpu); /** + * qemu_cpu_has_work: + * @cpu: The vCPU to check. + * + * Checks whether the CPU has work to do. + * + * Returns: %true if the CPU has work, %false otherwise. + */ +bool qemu_cpu_has_work(CPUState *cpu); + +/** * qemu_cpu_is_self: * @cpu: The vCPU to check against. * diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 62d2a66..11a19eb 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -19,7 +19,7 @@ * */ -#include "cpu-qom.h" +#include "cpu.h" #include "qemu-common.h" diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 99f9ee1..a43fb94 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -499,8 +499,10 @@ static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls) } #endif -static inline bool cpu_has_work(CPUAlphaState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUAlphaState *env = &ALPHA_CPU(cpu)->env; + /* Here we are checking to see if the CPU should wake up from HALT. We will have gotten into this state only for WTINT from PALmode. */ /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d01285f..d4a19be 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -551,8 +551,10 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } -static inline bool cpu_has_work(CPUARMState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUARMState *env = &ARM_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); } diff --git a/target-cris/cpu.h b/target-cris/cpu.h index a760367..2f71f63 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -283,8 +283,10 @@ static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc, #define cpu_list cris_cpu_list void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf); -static inline bool cpu_has_work(CPUCRISState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUCRISState *env = &CRIS_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index adc569c..bbe8de4 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1033,8 +1033,10 @@ static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp) #include "hw/apic.h" #endif -static inline bool cpu_has_work(CPUX86State *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUX86State *env = &X86_CPU(cpu)->env; + return ((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || (env->interrupt_request & (CPU_INTERRUPT_NMI | diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index da80469..7243b4f 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -253,8 +253,10 @@ static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc, *flags = 0; } -static inline bool cpu_has_work(CPULM32State *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPULM32State *env = &LM32_CPU(cpu)->env; + return env->interrupt_request & CPU_INTERRUPT_HARD; } diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 5e6ee50..780e2c9 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -257,8 +257,10 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ } -static inline bool cpu_has_work(CPUM68KState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUM68KState *env = &M68K_CPU(cpu)->env; + return env->interrupt_request & CPU_INTERRUPT_HARD; } diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index a570678..6131287 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -369,8 +369,10 @@ void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr, int is_write, int is_exec, int is_asi, int size); #endif -static inline bool cpu_has_work(CPUMBState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUMBState *env = &MICROBLAZE_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target-mips/cpu.h b/target-mips/cpu.h index ce3467f..9ce53da 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -706,16 +706,17 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } -static inline int cpu_has_work(CPUMIPSState *env) +static inline bool cpu_has_work(CPUState *cpu) { - int has_work = 0; + CPUMIPSState *env = &MIPS_CPU(cpu)->env; + bool has_work = false; /* It is implementation dependent if non-enabled interrupts wake-up the CPU, however most of the implementations only check for interrupts that can be taken. */ if ((env->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { - has_work = 1; + has_work = true; } /* MIPS-MT has the ability to halt the CPU. */ @@ -723,11 +724,11 @@ static inline int cpu_has_work(CPUMIPSState *env) /* The QEMU model will issue an _WAKE request whenever the CPUs should be woken up. */ if (env->interrupt_request & CPU_INTERRUPT_WAKE) { - has_work = 1; + has_work = true; } if (!mips_vpe_active(env)) { - has_work = 0; + has_work = false; } } return has_work; diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 9b38529..f1927d5 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2184,8 +2184,10 @@ static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn) extern void (*cpu_ppc_hypercall)(PowerPCCPU *); -static inline bool cpu_has_work(CPUPPCState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUPPCState *env = &POWERPC_CPU(cpu)->env; + return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD); } diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index c30ac3a..be13348 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -985,8 +985,10 @@ static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t pa cpu_interrupt(env, CPU_INTERRUPT_HARD); } -static inline bool cpu_has_work(CPUS390XState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUS390XState *env = &S390_CPU(cpu)->env; + return (env->interrupt_request & CPU_INTERRUPT_HARD) && (env->psw.mask & PSW_MASK_EXT); } diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index bf59222..fd6fb86 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -371,8 +371,10 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ } -static inline bool cpu_has_work(CPUSH4State *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUSH4State *env = &SUPERH_CPU(cpu)->env; + return env->interrupt_request & CPU_INTERRUPT_HARD; } diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index e16b7b3..e3b3b44 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -763,8 +763,10 @@ static inline bool tb_am_enabled(int tb_flags) #endif } -static inline bool cpu_has_work(CPUSPARCState *env1) +static inline bool cpu_has_work(CPUState *cpu) { + CPUSPARCState *env1 = &SPARC_CPU(cpu)->env; + return (env1->interrupt_request & CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(env1); } diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index de63f58..5467728 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -12,7 +12,7 @@ * or (at your option) any later version. */ -#include "cpu-qom.h" +#include "cpu.h" #include "qemu-common.h" static inline void set_feature(CPUUniCore32State *env, int feature) diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 81c14ff..2843a97 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -183,8 +183,10 @@ void uc32_translate_init(void); void do_interrupt(CPUUniCore32State *); void switch_mode(CPUUniCore32State *, int); -static inline bool cpu_has_work(CPUUniCore32State *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUUniCore32State *env = &UNICORE32_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); } diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 81f7833..fe4bd07 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -484,8 +484,10 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, #include "cpu-all.h" #include "exec-all.h" -static inline int cpu_has_work(CPUXtensaState *env) +static inline int cpu_has_work(CPUState *cpu) { + CPUXtensaState *env = &XTENSA_CPU(cpu)->env; + return env->pending_irq_level; }