| Message ID | 20081230201916.GA20059@oksana.dev.rtsoft.ru (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Kumar Gala |
| Headers | show |
On Dec 30, 2008, at 2:19 PM, Anton Vorontsov wrote: >>> >>> >>> + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; >>> + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; >> >> the size on the 0xb0000000 seems wrong > > This is how FSL U-Boots configure the cfg window, and I'm trying to > retain the compatibility. Anyway, now Linux maps only the first 4kB > of that area, so we don't actually care about this, but dts is still > correct for older u-boots. Newer U-Boots might want to correct this > value if they want to use other cfg window setup... I'd rather not pollute the .dts with this since I don't believe the open source u-boot supports PCIe on 83xx. - k
Dear Kumar, In message <1F7739C2-930B-49C1-B8FF-679AF1BBAEAE@kernel.crashing.org> you wrote: > > > This is how FSL U-Boots configure the cfg window, and I'm trying to > > retain the compatibility. Anyway, now Linux maps only the first 4kB > > of that area, so we don't actually care about this, but dts is still > > correct for older u-boots. Newer U-Boots might want to correct this > > value if they want to use other cfg window setup... > > I'd rather not pollute the .dts with this since I don't believe the > open source u-boot supports PCIe on 83xx. What exactly do you mean by "open source u-boot"? You don't really mean that there are propriatary (closed source) versions of U-Boot in Freescale, or are you? I iknow that you know that it's GPL, so I guess that was just an unlucky phrase? Best regards, Wolfgang Denk
On Wed, Dec 31, 2008 at 10:48:07AM -0600, Kumar Gala wrote: > > On Dec 30, 2008, at 2:19 PM, Anton Vorontsov wrote: > >>>> >>>> >>>> + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; >>>> + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; >>> >>> the size on the 0xb0000000 seems wrong >> >> This is how FSL U-Boots configure the cfg window, and I'm trying to >> retain the compatibility. Anyway, now Linux maps only the first 4kB >> of that area, so we don't actually care about this, but dts is still >> correct for older u-boots. Newer U-Boots might want to correct this >> value if they want to use other cfg window setup... > > I'd rather not pollute the .dts with this So you prefer to change the cfg window size to 0x1000? > since I don't believe the open > source u-boot supports PCIe on 83xx. Yes, that's correct. PCI-E support for community U-Boot is ongoing.
On Dec 31, 2008, at 11:10 AM, Wolfgang Denk wrote: > Dear Kumar, > > In message <1F7739C2-930B-49C1- > B8FF-679AF1BBAEAE@kernel.crashing.org> you wrote: >> >>> This is how FSL U-Boots configure the cfg window, and I'm trying to >>> retain the compatibility. Anyway, now Linux maps only the first 4kB >>> of that area, so we don't actually care about this, but dts is still >>> correct for older u-boots. Newer U-Boots might want to correct this >>> value if they want to use other cfg window setup... >> >> I'd rather not pollute the .dts with this since I don't believe the >> open source u-boot supports PCIe on 83xx. > > What exactly do you mean by "open source u-boot"? You don't really > mean that there are propriatary (closed source) versions of U-Boot in > Freescale, or are you? I iknow that you know that it's GPL, so I > guess that was just an unlucky phrase? I meant the official u-boot from denx.de vs the one FSL ships w/its boards & BSPs. The BSP u-boot has modifications that don't exist in the denx.de u-boot (as the quality of the code is not up to open source standards). That is all I meant. My statement was to convey that the kernel.org kernel should only worry itself with the denx.de u-boot (w/regards to compatibility). - k
On Dec 31, 2008, at 11:41 AM, Anton Vorontsov wrote: > On Wed, Dec 31, 2008 at 10:48:07AM -0600, Kumar Gala wrote: >> >> On Dec 30, 2008, at 2:19 PM, Anton Vorontsov wrote: >> >>>>> >>>>> >>>>> + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; >>>>> + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; >>>> >>>> the size on the 0xb0000000 seems wrong >>> >>> This is how FSL U-Boots configure the cfg window, and I'm trying to >>> retain the compatibility. Anyway, now Linux maps only the first 4kB >>> of that area, so we don't actually care about this, but dts is still >>> correct for older u-boots. Newer U-Boots might want to correct this >>> value if they want to use other cfg window setup... >> >> I'd rather not pollute the .dts with this > > So you prefer to change the cfg window size to 0x1000? I'd prefer to drop it (assuming that is reasonable). Does the PCI-express OF draft spec cover describing cfg space http://playground.sun.com/1275/proposals/New/516-it.txt - k
On Thu, Jan 01, 2009 at 08:29:39AM -0600, Kumar Gala wrote: [...] >>>>>> + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; >>>>>> + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; >>>>> >>>>> the size on the 0xb0000000 seems wrong >>>> >>>> This is how FSL U-Boots configure the cfg window, and I'm trying to >>>> retain the compatibility. Anyway, now Linux maps only the first 4kB >>>> of that area, so we don't actually care about this, but dts is still >>>> correct for older u-boots. Newer U-Boots might want to correct this >>>> value if they want to use other cfg window setup... >>> >>> I'd rather not pollute the .dts with this >> >> So you prefer to change the cfg window size to 0x1000? > > I'd prefer to drop it (assuming that is reasonable). I see. Yes, we can drop it and just read the outwin0 BAR register to find out the cfg space base address. > Does the PCI-express OF draft spec cover describing cfg space > > http://playground.sun.com/1275/proposals/New/516-it.txt If I understood correctly, the spec describes directly mapped cfg space, this won't work for 83xx PCI-E. I'll post new patches soon. Thanks,
On Thu, Jan 01, 2009 at 08:26:14AM -0600, Kumar Gala wrote: > I meant the official u-boot from denx.de vs the one FSL ships w/its > boards & BSPs. The BSP u-boot has modifications that don't exist in > the denx.de u-boot (as the quality of the code is not up to open > source standards). I believe "upstream" is the word you're looking for. > My statement was to convey that the kernel.org kernel should only > worry itself with the denx.de u-boot (w/regards to compatibility). Why? Unless the BSP u-boots do something insane, I think we should try to have the upstream kernel boot on the u-boot that comes on the board (it's not nice to require users to reflash unnecessarily). That said, the device tree should come from u-boot, not from the kernel. -Scott
On Mon, Jan 05, 2009 at 11:46:45AM -0600, Scott Wood wrote: [...] > > My statement was to convey that the kernel.org kernel should only > > worry itself with the denx.de u-boot (w/regards to compatibility). > > Why? Unless the BSP u-boots do something insane, I think we should try > to have the upstream kernel boot on the u-boot that comes on the board > (it's not nice to require users to reflash unnecessarily). Just in case, the latest version of this patch set is compatible with the FSL u-boots. Thanks,
Hello, On Mon, Jan 5, 2009 at 7:01 PM, Anton Vorontsov <avorontsov@ru.mvista.com> wrote: > On Mon, Jan 05, 2009 at 11:46:45AM -0600, Scott Wood wrote: > [...] >> > My statement was to convey that the kernel.org kernel should only >> > worry itself with the denx.de u-boot (w/regards to compatibility). >> >> Why? Unless the BSP u-boots do something insane, I think we should try >> to have the upstream kernel boot on the u-boot that comes on the board >> (it's not nice to require users to reflash unnecessarily). > The u-boot that came with the boards (at least MPC8315E-RDB) is too old for 2.6.25+ kernels: I have run into this earlier: http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06551.html Regards,
Hello Anton, On Mon, Jan 5, 2009 at 7:01 PM, Anton Vorontsov <avorontsov@ru.mvista.com> wrote: > On Mon, Jan 05, 2009 at 11:46:45AM -0600, Scott Wood wrote: >> >> Why? Unless the BSP u-boots do something insane, I think we should try >> to have the upstream kernel boot on the u-boot that comes on the board >> (it's not nice to require users to reflash unnecessarily). > > Just in case, the latest version of this patch set is compatible with > the FSL u-boots. > Up to now, I was testing PCIe with this combo: - U-Boot 1.3.0-rc2 (Nov 19 2007 - 16:37:36) MPC83XX, was on the board - dtc 1.1.0 - Linux 2.6.24.3 w/ Freescale patches from http://www.bitshrine.org/gpp/ That u-boot (i.e. on the mpc8315e-rdb board) had PCIe initialization. Is u-boot PCIe initialization required for this kernel patch to work? Regards,
On Tue, Jan 06, 2009 at 07:53:57PM +0100, Leon Woestenberg wrote: > Hello Anton, > > On Mon, Jan 5, 2009 at 7:01 PM, Anton Vorontsov > <avorontsov@ru.mvista.com> wrote: > > On Mon, Jan 05, 2009 at 11:46:45AM -0600, Scott Wood wrote: > >> > >> Why? Unless the BSP u-boots do something insane, I think we should try > >> to have the upstream kernel boot on the u-boot that comes on the board > >> (it's not nice to require users to reflash unnecessarily). > > > > Just in case, the latest version of this patch set is compatible with > > the FSL u-boots. > > > > Up to now, I was testing PCIe with this combo: > - U-Boot 1.3.0-rc2 (Nov 19 2007 - 16:37:36) MPC83XX, was on the board > - dtc 1.1.0 > - Linux 2.6.24.3 w/ Freescale patches from http://www.bitshrine.org/gpp/ > > > That u-boot (i.e. on the mpc8315e-rdb board) had PCIe initialization. > > Is u-boot PCIe initialization required for this kernel patch to work? Yup.
On Jan 6, 2009, at 1:27 PM, Anton Vorontsov wrote: > On Tue, Jan 06, 2009 at 07:53:57PM +0100, Leon Woestenberg wrote: >> Hello Anton, >> >> On Mon, Jan 5, 2009 at 7:01 PM, Anton Vorontsov >> <avorontsov@ru.mvista.com> wrote: >>> On Mon, Jan 05, 2009 at 11:46:45AM -0600, Scott Wood wrote: >>>> >>>> Why? Unless the BSP u-boots do something insane, I think we >>>> should try >>>> to have the upstream kernel boot on the u-boot that comes on the >>>> board >>>> (it's not nice to require users to reflash unnecessarily). >>> >>> Just in case, the latest version of this patch set is compatible >>> with >>> the FSL u-boots. >>> >> >> Up to now, I was testing PCIe with this combo: >> - U-Boot 1.3.0-rc2 (Nov 19 2007 - 16:37:36) MPC83XX, was on the board >> - dtc 1.1.0 >> - Linux 2.6.24.3 w/ Freescale patches from http://www.bitshrine.org/gpp/ >> >> >> That u-boot (i.e. on the mpc8315e-rdb board) had PCIe initialization. >> >> Is u-boot PCIe initialization required for this kernel patch to work? > > Yup. Really? what for? - k
On Tue, Jan 06, 2009 at 02:38:57PM -0600, Kumar Gala wrote: [...] >>>>> Why? Unless the BSP u-boots do something insane, I think we >>>>> should try >>>>> to have the upstream kernel boot on the u-boot that comes on the >>>>> board >>>>> (it's not nice to require users to reflash unnecessarily). >>>> >>>> Just in case, the latest version of this patch set is compatible >>>> with >>>> the FSL u-boots. >>>> >>> >>> Up to now, I was testing PCIe with this combo: >>> - U-Boot 1.3.0-rc2 (Nov 19 2007 - 16:37:36) MPC83XX, was on the board >>> - dtc 1.1.0 >>> - Linux 2.6.24.3 w/ Freescale patches from http://www.bitshrine.org/gpp/ >>> >>> >>> That u-boot (i.e. on the mpc8315e-rdb board) had PCIe initialization. >>> >>> Is u-boot PCIe initialization required for this kernel patch to work? >> >> Yup. > > Really? what for? Hm. U-Boot should initialize SerDes and PCI-E controller (pcie laws, inbound/outbound windows, clocks, etc.) Though if PCI-E controller wasn't initialized (i.e. board reflashed with the community u-boot), Linux just won't probe the pcie controller: cfg_bar = in_le32(hose->cfg_data + PEX_OUTWIN0_BAR); if (!cfg_bar) { /* PCI-E isn't configured. */ ret = -ENODEV; goto err1; } Or did I misunderstand the question?
Hello Anton, On Tue, Jan 6, 2009 at 10:15 PM, Anton Vorontsov <avorontsov@ru.mvista.com> wrote: > On Tue, Jan 06, 2009 at 02:38:57PM -0600, Kumar Gala wrote: >>>> Is u-boot PCIe initialization required for this kernel patch to work? >>> >>> Yup. >> >> Really? what for? > > Hm. U-Boot should initialize SerDes and PCI-E controller (pcie laws, > inbound/outbound windows, clocks, etc.) > > Though if PCI-E controller wasn't initialized (i.e. board reflashed > with the community u-boot), Linux just won't probe the pcie controller: > > cfg_bar = in_le32(hose->cfg_data + PEX_OUTWIN0_BAR); > if (!cfg_bar) { > /* PCI-E isn't configured. */ > ret = -ENODEV; > goto err1; > } > > Or did I misunderstand the question? > You understood correctly, thanks for answering. So to summarize, we need u-boot to initialize the PCIe controller, in order for Linux to further take it over. What u-boot versions/releases do provide this initialization? I know the u-boot with the board works, but it's incompatible with recent Linux kernels. Regards,
On Tue, Jan 06, 2009 at 11:33:35PM +0100, Leon Woestenberg wrote: > Hello Anton, > > On Tue, Jan 6, 2009 at 10:15 PM, Anton Vorontsov > <avorontsov@ru.mvista.com> wrote: > > On Tue, Jan 06, 2009 at 02:38:57PM -0600, Kumar Gala wrote: > >>>> Is u-boot PCIe initialization required for this kernel patch to work? > >>> > >>> Yup. > >> > >> Really? what for? > > > > Hm. U-Boot should initialize SerDes and PCI-E controller (pcie laws, > > inbound/outbound windows, clocks, etc.) > > > > Though if PCI-E controller wasn't initialized (i.e. board reflashed > > with the community u-boot), Linux just won't probe the pcie controller: > > > > cfg_bar = in_le32(hose->cfg_data + PEX_OUTWIN0_BAR); > > if (!cfg_bar) { > > /* PCI-E isn't configured. */ > > ret = -ENODEV; > > goto err1; > > } > > > > Or did I misunderstand the question? > > > You understood correctly, thanks for answering. > > So to summarize, we need u-boot to initialize the PCIe controller, in > order for Linux to further take it over. > > What u-boot versions/releases do provide this initialization? Only FSL U-Boots so far (i.e. community u-boot + fsl patches). > I know the u-boot with the board works, but it's incompatible with > recent Linux kernels. We should fix that (if possible).
Hello Anton, On Wed, Jan 7, 2009 at 12:42 AM, Anton Vorontsov <avorontsov@ru.mvista.com> wrote: > On Tue, Jan 06, 2009 at 11:33:35PM +0100, Leon Woestenberg wrote: >> So to summarize, we need u-boot to initialize the PCIe controller, in >> order for Linux to further take it over. >> >> What u-boot versions/releases do provide this initialization? > > Only FSL U-Boots so far (i.e. community u-boot + fsl patches). > Could you be more specific? I would like to test your Linux kernel patch for 83xx/PCIe mainlining. What version (and what patches) of u-boot do both initialize pcie *and* work with recent Linux kernels? I am aware of the latest MPC8315E BSP (~2008-06), bitshrine.org/gpp/, the 83xx git tree at denx, and master git. The first works with 2.6.24, but not with 2.6.25+ The patches at bitshrine are not newer than that. The tree's are not FSL, or is this the FSL U-Boot you mean? >> I know the u-boot with the board works, but it's incompatible with >> recent Linux kernels. > > We should fix that (if possible). > I was told "just to upgrade u-boot", not what the actual problem was, although I would like to learn that. http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06551.html Basically, this means I am unable to ship a bootloader now, supporting 2.6.24.7 now and 2.6.28 later. Regards,
On Tue, Jan 06, 2009 at 01:18:56PM +0100, Leon Woestenberg wrote: > Hello, > > On Mon, Jan 5, 2009 at 7:01 PM, Anton Vorontsov > <avorontsov@ru.mvista.com> wrote: > > On Mon, Jan 05, 2009 at 11:46:45AM -0600, Scott Wood wrote: > > [...] > >> > My statement was to convey that the kernel.org kernel should only > >> > worry itself with the denx.de u-boot (w/regards to compatibility). > >> > >> Why? Unless the BSP u-boots do something insane, I think we should try > >> to have the upstream kernel boot on the u-boot that comes on the board > >> (it's not nice to require users to reflash unnecessarily). > > > > The u-boot that came with the boards (at least MPC8315E-RDB) is too > old for 2.6.25+ kernels: > > I have run into this earlier: > > http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06551.html "It doesn't work" doesn't imply "It's worthless to try to make it work". -Scott
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts index d3d3097..eb3c4ad 100644 --- a/arch/powerpc/boot/dts/mpc8315erdb.dts +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts @@ -22,6 +22,8 @@ serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; }; cpus { @@ -330,4 +332,70 @@ compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; + + pci1: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 8 + 0 0 0 2 &ipic 1 8 + 0 0 0 3 &ipic 1 8 + 0 0 0 4 &ipic 1 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; + + pci2: pcie@e000a000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; + reg = <0xe000a000 0x00001000 0xd0000000 0x01000000>; + ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 2 8 + 0 0 0 2 &ipic 2 8 + 0 0 0 3 &ipic 2 8 + 0 0 0 4 &ipic 2 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xc0000000 + 0x02000000 0 0xc0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; }; diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index 0484561..902d8f2 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts @@ -23,6 +23,8 @@ serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; }; cpus { @@ -390,4 +392,70 @@ compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; + + pci1: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 8 + 0 0 0 2 &ipic 1 8 + 0 0 0 3 &ipic 1 8 + 0 0 0 4 &ipic 1 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; + + pci2: pcie@e000a000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; + reg = <0xe000a000 0x00001000 0xd0000000 0x01000000>; + ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 2 8 + 0 0 0 2 &ipic 2 8 + 0 0 0 3 &ipic 2 8 + 0 0 0 4 &ipic 2 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xc0000000 + 0x02000000 0 0xc0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; }; diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts index 9fe8e4c..cfed419 100644 --- a/arch/powerpc/boot/dts/mpc8377_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts @@ -22,6 +22,8 @@ serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; }; cpus { @@ -331,4 +333,70 @@ compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; + + pci1: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 8 + 0 0 0 2 &ipic 1 8 + 0 0 0 3 &ipic 1 8 + 0 0 0 4 &ipic 1 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; + + pci2: pcie@e000a000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; + reg = <0xe000a000 0x00001000 0xd0000000 0x01000000>; + ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 2 8 + 0 0 0 2 &ipic 2 8 + 0 0 0 3 &ipic 2 8 + 0 0 0 4 &ipic 2 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xc0000000 + 0x02000000 0 0xc0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; }; diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts index 67a08d2..67d0802 100644 --- a/arch/powerpc/boot/dts/mpc8378_mds.dts +++ b/arch/powerpc/boot/dts/mpc8378_mds.dts @@ -23,6 +23,8 @@ serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; }; cpus { @@ -376,4 +378,70 @@ compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; + + pci1: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 8 + 0 0 0 2 &ipic 1 8 + 0 0 0 3 &ipic 1 8 + 0 0 0 4 &ipic 1 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; + + pci2: pcie@e000a000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; + reg = <0xe000a000 0x00001000 0xd0000000 0x01000000>; + ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 2 8 + 0 0 0 2 &ipic 2 8 + 0 0 0 3 &ipic 2 8 + 0 0 0 4 &ipic 2 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xc0000000 + 0x02000000 0 0xc0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; }; diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts index 3a6d528..287e0b2 100644 --- a/arch/powerpc/boot/dts/mpc8378_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts @@ -22,6 +22,8 @@ serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; }; cpus { @@ -317,4 +319,70 @@ compatible = "fsl,mpc8349-pci"; device_type = "pci"; }; + + pci1: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000 0xb0000000 0x01000000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 8 + 0 0 0 2 &ipic 1 8 + 0 0 0 3 &ipic 1 8 + 0 0 0 4 &ipic 1 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; + + pci2: pcie@e000a000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; + reg = <0xe000a000 0x00001000 0xd0000000 0x01000000>; + ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 2 8 + 0 0 0 2 &ipic 2 8 + 0 0 0 3 &ipic 2 8 + 0 0 0 4 &ipic 2 8>; + clock-frequency = <0>; + /* cleared by u-boot */ + status = "not configured"; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xc0000000 + 0x02000000 0 0xc0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; }; diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c index 5177bdd..b690fd7 100644 --- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c @@ -38,6 +38,8 @@ static void __init mpc831x_rdb_setup_arch(void) #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); + for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie") + mpc83xx_add_bridge(np); #endif mpc831x_usb_cfg(); } diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c index 530ef99..634785c 100644 --- a/arch/powerpc/platforms/83xx/mpc837x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c @@ -84,14 +84,10 @@ static void __init mpc837x_mds_setup_arch(void) ppc_md.progress("mpc837x_mds_setup_arch()", 0); #ifdef CONFIG_PCI - for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") { - if (!of_device_is_available(np)) { - pr_warning("%s: disabled by the firmware.\n", - np->full_name); - continue; - } + for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") + mpc83xx_add_bridge(np); + for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie") mpc83xx_add_bridge(np); - } #endif mpc837xmds_usb_cfg(); } diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c index 1d09654..3d7b953 100644 --- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c @@ -38,6 +38,8 @@ static void __init mpc837x_rdb_setup_arch(void) #ifdef CONFIG_PCI for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") mpc83xx_add_bridge(np); + for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie") + mpc83xx_add_bridge(np); #endif mpc837x_usb_cfg(); }