| Message ID | 1337681007-22709-6-git-send-email-lokeshvutla@ti.com |
|---|---|
| State | Accepted |
| Commit | 784ab7c545d25288a82216d18e2b0ca3beae470b |
| Delegated to: | Tom Rini |
| Headers | show |
On Tue, May 22, 2012 at 03:33:25PM +0530, Lokesh Vutla wrote: > In OMAP5432 EMIF controlller supports DDR3 device. > This patch adds support for ddr3 device intialization and configuration. > Initialization sequence is done as specified in JEDEC specs. > This also adds support for ddr3 leveling. [snip] > @@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) > * Changing the timing registers in EMIF can happen(going from one > * OPP to another) > */ > - if (!in_sdram) > - lpddr2_init(base, regs); > + if (!in_sdram) { > + if (omap_revision() != OMAP5432_ES1_0) > + lpddr2_init(base, regs); > + else > + ddr3_init(base, regs); > + } In omap4+ land do we have any other way of telling which family we're on? I ask since I'm preparing to add DDR3 support to am33xx and I'd like to switch it over to the common emif framework as well.
Hi Tom, >> In OMAP5432 EMIF controlller supports DDR3 device. >> This patch adds support for ddr3 device intialization and configuration. >> Initialization sequence is done as specified in JEDEC specs. >> This also adds support for ddr3 leveling. > [snip] >> @@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) >> * Changing the timing registers in EMIF can happen(going from one >> * OPP to another) >> */ >> - if (!in_sdram) >> - lpddr2_init(base, regs); >> + if (!in_sdram) { >> + if (omap_revision() != OMAP5432_ES1_0) >> + lpddr2_init(base, regs); >> + else >> + ddr3_init(base, regs); >> + } > > In omap4+ land do we have any other way of telling which family we're > on? I ask since I'm preparing to add DDR3 support to am33xx and I'd > like to switch it over to the common emif framework as well. > I think the SDRAM_TYPE[31:29] EMIF_SDRAM_CONFIG register should tell the connected device at reset. I will cross confirm this on the board and tell. That being true, we can get rid of these OMAP based checks and have generic code. Thanks, Sricharan
On Tue, May 22, 2012 at 08:28:55PM +0530, R, Sricharan wrote: > Hi Tom, > >> In OMAP5432 EMIF controlller supports DDR3 device. > >> This patch adds support for ddr3 device intialization and configuration. > >> Initialization sequence is done as specified in JEDEC specs. > >> This also adds support for ddr3 leveling. > > [snip] > >> @@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) > >> ? ? ? ?* Changing the timing registers in EMIF can happen(going from one > >> ? ? ? ?* OPP to another) > >> ? ? ? ?*/ > >> - ? ? if (!in_sdram) > >> - ? ? ? ? ? ? lpddr2_init(base, regs); > >> + ? ? if (!in_sdram) { > >> + ? ? ? ? ? ? if (omap_revision() != OMAP5432_ES1_0) > >> + ? ? ? ? ? ? ? ? ? ? lpddr2_init(base, regs); > >> + ? ? ? ? ? ? else > >> + ? ? ? ? ? ? ? ? ? ? ddr3_init(base, regs); > >> + ? ? } > > > > In omap4+ land do we have any other way of telling which family we're > > on? ?I ask since I'm preparing to add DDR3 support to am33xx and I'd > > like to switch it over to the common emif framework as well. > > > I think the SDRAM_TYPE[31:29] EMIF_SDRAM_CONFIG > register should tell the connected device at reset. > I will cross confirm this on the board and tell. OK. I can't find the omap5430 TRM quickly but on the am335x one, SDRAM_TYPE is 3 for DDR3, 2 for DDR2 and 1 for LPDDR1 and 0 for DDR1.
>> >> - ? ? if (!in_sdram) >> >> - ? ? ? ? ? ? lpddr2_init(base, regs); >> >> + ? ? if (!in_sdram) { >> >> + ? ? ? ? ? ? if (omap_revision() != OMAP5432_ES1_0) >> >> + ? ? ? ? ? ? ? ? ? ? lpddr2_init(base, regs); >> >> + ? ? ? ? ? ? else >> >> + ? ? ? ? ? ? ? ? ? ? ddr3_init(base, regs); >> >> + ? ? } >> > >> > In omap4+ land do we have any other way of telling which family we're >> > on? ?I ask since I'm preparing to add DDR3 support to am33xx and I'd >> > like to switch it over to the common emif framework as well. >> > >> I think the SDRAM_TYPE[31:29] EMIF_SDRAM_CONFIG >> register should tell the connected device at reset. >> I will cross confirm this on the board and tell. > > OK. I can't find the omap5430 TRM quickly but on the am335x one, > SDRAM_TYPE is 3 for DDR3, 2 for DDR2 and 1 for LPDDR1 and 0 for DDR1. ah, this is what is there on OMAP5. 3 for DDR3 4 for LPDDR2-S4, 5 for LPDDR2-S2 Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 in same way. Is the reset value set correctly on am335x according to the device connected? Thanks, Sricharan
On 05/22/2012 08:27 AM, R, Sricharan wrote: >>>>> - ? ? if (!in_sdram) >>>>> - ? ? ? ? ? ? lpddr2_init(base, regs); >>>>> + ? ? if (!in_sdram) { >>>>> + ? ? ? ? ? ? if (omap_revision() != OMAP5432_ES1_0) >>>>> + ? ? ? ? ? ? ? ? ? ? lpddr2_init(base, regs); >>>>> + ? ? ? ? ? ? else >>>>> + ? ? ? ? ? ? ? ? ? ? ddr3_init(base, regs); >>>>> + ? ? } >>>> >>>> In omap4+ land do we have any other way of telling which family we're >>>> on? ?I ask since I'm preparing to add DDR3 support to am33xx and I'd >>>> like to switch it over to the common emif framework as well. >>>> >>> I think the SDRAM_TYPE[31:29] EMIF_SDRAM_CONFIG >>> register should tell the connected device at reset. >>> I will cross confirm this on the board and tell. >> >> OK. I can't find the omap5430 TRM quickly but on the am335x one, >> SDRAM_TYPE is 3 for DDR3, 2 for DDR2 and 1 for LPDDR1 and 0 for DDR1. > > ah, this is what is there on OMAP5. > 3 for DDR3 > 4 for LPDDR2-S4, > 5 for LPDDR2-S2 4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73 > Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 > in same way. > Is the reset value set correctly on am335x according to the device connected? I'll have to do some checking as the code doesn't check that today.
Hi Tom, >> >> ah, this is what is there on OMAP5. >> 3 for DDR3 >> 4 for LPDDR2-S4, >> 5 for LPDDR2-S2 > > > 4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73 > > >> Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 >> in same way. >> Is the reset value set correctly on am335x according to the device >> connected? > > > I'll have to do some checking as the code doesn't check that today. > The reset value reflects the connected device correctly for lpddr2 and ddr3. Is that the same case in am33xx platforms ? Thanks, Sricharan
On 05/23/2012 05:22 AM, R, Sricharan wrote: > Hi Tom, >>> >>> ah, this is what is there on OMAP5. >>> 3 for DDR3 >>> 4 for LPDDR2-S4, >>> 5 for LPDDR2-S2 >> >> >> 4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73 >> >> >>> Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 >>> in same way. >>> Is the reset value set correctly on am335x according to the device >>> connected? >> >> >> I'll have to do some checking as the code doesn't check that today. >> > The reset value reflects the connected device correctly for lpddr2 and ddr3. > Is that the same case in am33xx platforms ? Yes, it's 3 on DDR3 and 2 on (non-LP) DDR2. I spent some time yesterday starting on splitting up emif-common (am33xx does not have DMM) and making am33xx link at least with the common code. My idea is to add a few more defines and make that part of do_sdram_init be: if (!in_sdram) { switch(reg_sdram_type) { #ifdef CONFIG_EMIF4_DDR2 case 2: ddr2_init(); break; #ifdef CONFIG_EMFI4_DDR3 case 3: ddr3_init(); break; #endif #ifdef CONFIG_EMIF4_LPDDR2 case 4: case 5: lpddr2_init(); break; #endif default: panic("Unsupported DDR type connected to EMIF4"); } } And move lpddr2_init to emif4-lpddr2.c, and so forth. My experimenting yesterday lead me to conclude that EMIF_MOD_ID_REGISTER behaves as is documented for am33xx on omap4/5 so what we're doing should be feasible. I'm going to try and locally make the ddr3 patches work on the am33xx DDR3 board as a way to prove that out and if it works, and we're fine with what I've laid out above, start working towards that layout.
Hi Tom, >>>> ah, this is what is there on OMAP5. >>>> 3 for DDR3 >>>> 4 for LPDDR2-S4, >>>> 5 for LPDDR2-S2 >>> >>> >>> >>> 4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73 >>> >>> >>>> Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 >>>> in same way. >>>> Is the reset value set correctly on am335x according to the device >>>> connected? >>> >>> >>> >>> I'll have to do some checking as the code doesn't check that today. >>> >> The reset value reflects the connected device correctly for lpddr2 and >> ddr3. >> Is that the same case in am33xx platforms ? > > > Yes, it's 3 on DDR3 and 2 on (non-LP) DDR2. I spent some time yesterday > starting on splitting up emif-common (am33xx does not have DMM) and making > am33xx link at least with the common code. My idea is to add a few more > defines and make that part of do_sdram_init be: > if (!in_sdram) { > switch(reg_sdram_type) { > #ifdef CONFIG_EMIF4_DDR2 > case 2: > ddr2_init(); > break; > #ifdef CONFIG_EMFI4_DDR3 > case 3: > ddr3_init(); > break; > #endif > #ifdef CONFIG_EMIF4_LPDDR2 > case 4: > case 5: > lpddr2_init(); > break; > #endif > default: > panic("Unsupported DDR type connected to EMIF4"); > } > } > > And move lpddr2_init to emif4-lpddr2.c, and so forth. My experimenting > yesterday lead me to conclude that EMIF_MOD_ID_REGISTER behaves as is > documented for am33xx on omap4/5 so what we're doing should be feasible. ok, and there are only few omap checks that are in the common lpddr2 and ddr3 init paths, that we should be able to get rid of, so we can have generic lpddr2_init and ddr3_init. But anyways as you said we can do all these only after the current code works for DDR3 on your am33xx. > I'm going to try and locally make the ddr3 patches work on the am33xx DDR3 > board as a way to prove that out and if it works, and we're fine with what > I've laid out above, start working towards that layout. > yeah, sounds correct. How about something like this, similar to the above #define DDR2 1 #define LPDDR2 2 #define DDR3 3 #define LPDDR3 4 and soc specific code returns the correct ddr type. For OMAP get_ddr_type() { switch(EMIF_SDRAM_CONFIG & SDRAM_TYPE) { case 3: return DDR3; case 4: case 5: default: return LPDDR2; } We can avoid the #ifdef s in the emif code and use the type returned by SOC to do the required initialisations. ? Thanks, Sricharan
On Thu, May 24, 2012 at 12:15:23PM +0530, R, Sricharan wrote: > Hi Tom, [snip] > > ?I'm going to try and locally make the ddr3 patches work on the am33xx DDR3 > > board as a way to prove that out and if it works, and we're fine with what > > I've laid out above, start working towards that layout. > > > yeah, sounds correct. > How about something like this, similar to the above > #define DDR2 1 > #define LPDDR2 2 > #define DDR3 3 > #define LPDDR3 4 > > and soc specific code returns the correct ddr type. For OMAP > get_ddr_type() > { > switch(EMIF_SDRAM_CONFIG & SDRAM_TYPE) { > case 3: > return DDR3; > case 4: > case 5: > default: > return LPDDR2; > } > We can avoid the #ifdef s in the emif code and use the type returned by > SOC to do the required initialisations. ? One thing I want to avoid is bloating each of the boards with DDR config code it won't ever use. OMAP4/5 won't have DDR2 and AM33xx won't have LPDDR2. But maybe there's some linker magic we can do to avoid #ifdefs.
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index db509c9..0668fe4 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -190,7 +190,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - if (omap_revision() == OMAP5430_ES1_0) { + if (omap_revision() >= OMAP5430_ES1_0) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -202,6 +202,101 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) } } +static void ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* keep sdram in self-refresh */ + writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + __udelay(130); + + /* + * Set invert_clkout (if activated)--DDR_PHYCTRL_1 + * Invert clock adds an additional half cycle delay on the command + * interface. The additional half cycle, is usually meant to enable + * leveling in the situation that DQS is later than CK on the board.It + * also helps provide some additional margin for leveling. + */ + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + __udelay(130); + + writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + + /* Launch Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + /* Wait till full leveling is complete */ + readl(&emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Read data eye leveling no of samples */ + config_data_eye_leveling_samples(base); + + /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */ + writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Launch Incremental leveling */ + writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); +} + +static void ddr3_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; + + /* + * Set SDRAM_CONFIG and PHY control registers to locked frequency + * and RL =7. As the default values of the Mode Registers are not + * defined, contents of mode Registers must be fully initialized. + * H/W takes care of this initialization + */ + writel(regs->sdram_config_init, &emif->emif_sdram_config); + + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + /* Update timing registers */ + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ddr3_ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ddr3_ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + } + + /* enable leveling */ + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + + ddr3_leveling(base, regs); +} + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) @@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ - if (!in_sdram) - lpddr2_init(base, regs); + if (!in_sdram) { + if (omap_revision() != OMAP5432_ES1_0) + lpddr2_init(base, regs); + else + ddr3_init(base, regs); + } /* Write to the shadow registers */ emif_update_timings(base, regs); diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 187e938..2c34e48 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -118,6 +118,11 @@ void do_io_settings(void) } #endif +/* dummy fuction for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ +} + void init_omap_revision(void) { /* diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index df0b760..d0c3ff7 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -35,6 +35,7 @@ #include <asm/sizes.h> #include <asm/utils.h> #include <asm/arch/gpio.h> +#include <asm/emif.h> DECLARE_GLOBAL_DATA_PTR; @@ -203,6 +204,20 @@ void do_io_settings(void) } #endif +void config_data_eye_leveling_samples(u32 emif_base) +{ + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ + if (emif_base == EMIF1_BASE) + writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + &(ioregs_base->control_emif1_sdram_config_ext)); + else if (emif_base == EMIF2_BASE) + writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + &(ioregs_base->control_emif2_sdram_config_ext)); +} + void init_omap_revision(void) { /* diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 5d2649e..c2ad877 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -471,6 +471,49 @@ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) +/*EMIF_READ_WRITE_LEVELING_CONTROL*/ +#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 +#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ +#define EMIF_REG_RDWRLVL_EN_SHIFT 31 +#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ +#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 +#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) + +/*Leveling Fields */ +#define DDR3_WR_LVL_INT 0x73 +#define DDR3_RD_LVL_INT 0x33 +#define DDR3_RD_LVL_GATE_INT 0x59 +#define RD_RW_LVL_INC_PRE 0x0 +#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) + +#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ + | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ + | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ + | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) + +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 +#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 + /* DMM */ #define DMM_BASE 0x4E000040 @@ -1104,5 +1147,5 @@ extern u32 *const T_den; extern u32 *const emif_sizes; #endif - +void config_data_eye_leveling_samples(u32 emif_base); #endif
In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> --- arch/arm/cpu/armv7/omap-common/emif-common.c | 105 +++++++++++++++++++++++++- arch/arm/cpu/armv7/omap4/hwinit.c | 5 + arch/arm/cpu/armv7/omap5/hwinit.c | 15 ++++ arch/arm/include/asm/emif.h | 45 +++++++++++- 4 files changed, 166 insertions(+), 4 deletions(-)