From patchwork Sat May 19 01:53:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 160166 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B2320B6FCA for ; Sat, 19 May 2012 12:08:33 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E470128081; Sat, 19 May 2012 04:08:29 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VsDxRW04L7HK; Sat, 19 May 2012 04:08:29 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AE96F28082; Sat, 19 May 2012 04:08:27 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D380628082 for ; Sat, 19 May 2012 04:08:24 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LvAe2BaZCqVE for ; Sat, 19 May 2012 04:08:23 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe002.messaging.microsoft.com [213.199.154.205]) by theia.denx.de (Postfix) with ESMTPS id 1BBAC28081 for ; Sat, 19 May 2012 04:08:21 +0200 (CEST) Received: from mail2-am1-R.bigfish.com (10.3.201.243) by AM1EHSOBE004.bigfish.com (10.3.204.24) with Microsoft SMTP Server id 14.1.225.23; Sat, 19 May 2012 01:53:06 +0000 Received: from mail2-am1 (localhost [127.0.0.1]) by mail2-am1-R.bigfish.com (Postfix) with ESMTP id A90652202ED for ; Sat, 19 May 2012 01:53:06 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -4 X-BigFish: VS-4(zz98aLzz1202hzz8275bhz2dh2a8h668h839hd24he5bhf0ah) Received: from mail2-am1 (localhost.localdomain [127.0.0.1]) by mail2-am1 (MessageSwitch) id 1337392385604179_13354; Sat, 19 May 2012 01:53:05 +0000 (UTC) Received: from AM1EHSMHS016.bigfish.com (unknown [10.3.201.248]) by mail2-am1.bigfish.com (Postfix) with ESMTP id 91A323E0048 for ; Sat, 19 May 2012 01:53:05 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS016.bigfish.com (10.3.207.154) with Microsoft SMTP Server (TLS) id 14.1.225.23; Sat, 19 May 2012 01:53:05 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.298.5; Fri, 18 May 2012 20:53:12 -0500 Received: from localhost.localdomain ([10.214.82.34]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q4J1rBqp007853; Fri, 18 May 2012 18:53:12 -0700 From: York Sun To: Date: Fri, 18 May 2012 18:53:11 -0700 Message-ID: <1337392391-26822-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH] powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Workaround for erratum NMG_CPU_A011 can be enabled by hwconfig with syntax fsl_cpu_a011:enable This workaround is not enabled by default. Enabling this workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 6 +++++- arch/powerpc/cpu/mpc85xx/cpu_init.c | 24 +++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/release.S | 15 +++++++++++++++ 3 files changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 4e1a54a..858b3f8 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -27,6 +27,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + extern int enable_cpu_a011_workaround; +#endif __maybe_unused u32 svr = get_svr(); #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) @@ -56,8 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * The SVR has been checked by cpu_init_r(). */ - if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) + if (enable_cpu_a011_workaround) puts("Work-around for Erratum CPU-A011 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4f03d25..10f142e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -47,6 +48,8 @@ #include "../../../../drivers/block/fsl_sata.h" +#define HWCONFIG_BUFFER_SIZE 128 + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE @@ -311,11 +314,30 @@ int cpu_init_r(void) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* + * CPU22 and NMG_CPU_A011 share the same workaround. * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * NMG_CPU_A011 is activated by hwconfig with syntax: + * fsl_cpu_a011:enable */ - if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) { + extern int enable_cpu_a011_workaround; +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3); +#else + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; + + if (hwconfig_arg_cmp_f("fsl_cpu_a011", "enable", buf) > 0) { + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3); + } +#endif + if (enable_cpu_a011_workaround) { flush_dcache(); mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); sync(); diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 1860684..b8d4a37 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -163,6 +163,12 @@ __secondary_start_page: cmpw r3,r5 bge 2f 1: +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + lis r3,toreset(enable_cpu_a011_workaround)@ha + lwz r3,toreset(enable_cpu_a011_workaround)@l(r3) + cmpwi r3,0 + beq 2f +#endif mfspr r3,L1CSR2 oris r3,r3,(L1CSR2_DCWS)@h mtspr L1CSR2,r3 @@ -346,6 +352,15 @@ __bootpg_addr: __spin_table: .space CONFIG_MAX_CPUS*ENTRY_SIZE + /* + * This variable is set by cpu_init_r() after parsing hwconfig + * to enable workaround for erratum NMG_CPU_A011. + */ + .align L1_CACHE_SHIFT + .global enable_cpu_a011_workaround +enable_cpu_a011_workaround: + .long 0 + /* Fill in the empty space. The actual reset vector is * the last word of the page */ __secondary_start_code_end: