| Message ID | 1337343153-3019-2-git-send-email-rajeshwari.s@samsung.com |
|---|---|
| State | Superseded |
| Delegated to: | Heiko Schocher |
| Headers | show |
Hi, On Fri, May 18, 2012 at 5:12 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com > wrote: > This adds i2c clock information for EXYNOS5. > > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> > Signed-off-by: Doug Anderson <dianders@chromium.org> > Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> > Just a few nits, otherwise: Acked-by: Simon Glass <sjg@chromium.org> > --- > arch/arm/cpu/armv7/exynos/clock.c | 33 > ++++++++++++++++++++++++++++++++ > arch/arm/include/asm/arch-exynos/clk.h | 1 + > 2 files changed, 34 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c > b/arch/arm/cpu/armv7/exynos/clock.c > index 330bd75..3b86b0c 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void) > writel(cfg, &clk->div_lcd0); > } > > +/* > + * I2C > + * > + * exynos5: obtaining the I2C clock > + */ > +static unsigned long exynos5_get_i2c_clk(void) > +{ > + struct exynos5_clock *clk = > + (struct exynos5_clock *)samsung_get_base_clock(); > + unsigned long aclk_66, aclk_66_pre, sclk; > + unsigned int ratio; > + > + sclk = get_pll_clk(MPLL); > + > + ratio = ((readl(&clk->div_top1)) >> 24); > Remove extra brackets around this > + ratio &= (0x7); > + aclk_66_pre = sclk/(ratio+1); > + ratio = readl(&clk->div_top0); > + ratio &= (0x7); > + aclk_66 = aclk_66_pre/(ratio+1); > + return aclk_66; > +} > + > unsigned long get_pll_clk(int pllreg) > { > if (cpu_is_exynos5()) > @@ -594,6 +617,16 @@ unsigned long get_arm_clk(void) > return exynos4_get_arm_clk(); > } > > +unsigned long get_i2c_clk(void) > +{ > + if (cpu_is_exynos5()) { > + return exynos5_get_i2c_clk(); > + } else { > + debug("I2C clock is not set for this CPU\n"); > + return 0; > I think the return 0 needs a tab > + } > +} > + > unsigned long get_pwm_clk(void) > { > if (cpu_is_exynos5()) > diff --git a/arch/arm/include/asm/arch-exynos/clk.h > b/arch/arm/include/asm/arch-exynos/clk.h > index 637fb4b..72dc655 100644 > --- a/arch/arm/include/asm/arch-exynos/clk.h > +++ b/arch/arm/include/asm/arch-exynos/clk.h > @@ -30,6 +30,7 @@ > > unsigned long get_pll_clk(int pllreg); > unsigned long get_arm_clk(void); > +unsigned long get_i2c_clk(void); > unsigned long get_pwm_clk(void); > unsigned long get_uart_clk(int dev_index); > void set_mmc_clk(int dev_index, unsigned int div); > -- > 1.7.4.4 > >
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..3b86b0c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); } +/* + * I2C + * + * exynos5: obtaining the I2C clock + */ +static unsigned long exynos5_get_i2c_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long aclk_66, aclk_66_pre, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + + ratio = ((readl(&clk->div_top1)) >> 24); + ratio &= (0x7); + aclk_66_pre = sclk/(ratio+1); + ratio = readl(&clk->div_top0); + ratio &= (0x7); + aclk_66 = aclk_66_pre/(ratio+1); + return aclk_66; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -594,6 +617,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); } +unsigned long get_i2c_clk(void) +{ + if (cpu_is_exynos5()) { + return exynos5_get_i2c_clk(); + } else { + debug("I2C clock is not set for this CPU\n"); + return 0; + } +} + unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..72dc655 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -30,6 +30,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);