Patchwork [U-Boot,V2,2/2] spi: Tegra2: Seaboard: enable SPI/UART corruption fix

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Submitter Tom Warren
Date May 15, 2012, 10:32 p.m.
Message ID <1337121157-15284-2-git-send-email-twarren@nvidia.com>
Download mbox | patch
Permalink /patch/159467/
State Accepted
Commit 046c76a6c0af77952a1ec5ab576d12f93ed52641
Headers show

Comments

Tom Warren - May 15, 2012, 10:32 p.m.
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
v2: Split config file changes into separate commit

 include/configs/seaboard.h |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)
Simon Glass - May 31, 2012, 11:27 p.m.
On Tue, May 15, 2012 at 3:32 PM, Tom Warren <twarren.nvidia@gmail.com>wrote:

> Signed-off-by: Tom Warren <twarren@nvidia.com>
>

Acked-by: Simon Glass <sjg@chromium.org>

(although later in your series this actually gets reverted)

---
> v2: Split config file changes into separate commit
>
>  include/configs/seaboard.h |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)
>
> diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
> index 46d4228..889bdff 100644
> --- a/include/configs/seaboard.h
> +++ b/include/configs/seaboard.h
> @@ -52,6 +52,15 @@
>
>  /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
>  #define CONFIG_UART_DISABLE_GPIO       GPIO_PI3
> +/*
> + * On Seaboard, SPIFLASH is muxed with UART4. The next 5 defines are
> + * needed to work around that design error.
> + */
> +#define CONFIG_SPI_UART_SWITCH
> +#define CONFIG_SPI_CORRUPTS_UART       NV_PA_APB_UARTD_BASE
> +#define CONFIG_SPI_CORRUPTS_UART_NR    3
> +#define CONFIG_SPI_CORRUPTS_UART_DLY   2500
> +#undef CONFIG_CMDLINE_EDITING          /* avoid NUL in input buffer */
>
>  #define CONFIG_MACH_TYPE               MACH_TYPE_SEABOARD
>  #define CONFIG_SYS_BOARD_ODMDATA       0x300d8011 /* lp1, 1GB */
> --
> 1.7.0.4
>
>

Patch

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 46d4228..889bdff 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -52,6 +52,15 @@ 
 
 /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
 #define CONFIG_UART_DISABLE_GPIO	GPIO_PI3
+/*
+ * On Seaboard, SPIFLASH is muxed with UART4. The next 5 defines are
+ * needed to work around that design error.
+ */
+#define CONFIG_SPI_UART_SWITCH
+#define CONFIG_SPI_CORRUPTS_UART	NV_PA_APB_UARTD_BASE
+#define CONFIG_SPI_CORRUPTS_UART_NR	3
+#define CONFIG_SPI_CORRUPTS_UART_DLY	2500
+#undef CONFIG_CMDLINE_EDITING		/* avoid NUL in input buffer */
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_SEABOARD
 #define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */