From patchwork Tue May 15 18:01:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 159404 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B7888B6F9F for ; Wed, 16 May 2012 04:01:41 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2BA9828094; Tue, 15 May 2012 20:01:40 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kzYqD6cco1ge; Tue, 15 May 2012 20:01:39 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EF03928089; Tue, 15 May 2012 20:01:37 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1AD8F28089 for ; Tue, 15 May 2012 20:01:34 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FDv-YD8bxW29 for ; Tue, 15 May 2012 20:01:33 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe006.messaging.microsoft.com [216.32.181.186]) by theia.denx.de (Postfix) with ESMTPS id 7962E28088 for ; Tue, 15 May 2012 20:01:30 +0200 (CEST) Received: from mail12-ch1-R.bigfish.com (10.43.68.229) by CH1EHSOBE006.bigfish.com (10.43.70.56) with Microsoft SMTP Server id 14.1.225.23; Tue, 15 May 2012 18:01:22 +0000 Received: from mail12-ch1 (localhost [127.0.0.1]) by mail12-ch1-R.bigfish.com (Postfix) with ESMTP id 6CFDC34059A; Tue, 15 May 2012 18:01:22 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839hd24he5bh) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail12-ch1 (localhost.localdomain [127.0.0.1]) by mail12-ch1 (MessageSwitch) id 133710488068856_7532; Tue, 15 May 2012 18:01:20 +0000 (UTC) Received: from CH1EHSMHS004.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.245]) by mail12-ch1.bigfish.com (Postfix) with ESMTP id 0160318009C; Tue, 15 May 2012 18:01:19 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS004.bigfish.com (10.43.70.4) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 15 May 2012 18:01:18 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.298.5; Tue, 15 May 2012 13:01:23 -0500 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.240.143]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q4FI1LJC013831; Tue, 15 May 2012 11:01:22 -0700 From: Fabio Estevam To: Date: Tue, 15 May 2012 15:01:16 -0300 Message-ID: <1337104876-15529-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Fabio Estevam Subject: [U-Boot] [PATCH v2 1/3] mx53: Allow IPUv3 driver to also work on mx53 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam --- Changes since v1: - Properly implement the IPU offset scheme. arch/arm/include/asm/arch-mx5/imx-regs.h | 8 ++++- drivers/video/ipu_regs.h | 42 +++++++++++++++--------------- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index cef4190..88fb7cb 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -25,7 +25,8 @@ #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ -#define IPU_CTRL_BASE_ADDR 0x40000000 +#define IPU_SOC_BASE_ADDR 0x40000000 +#define IPU_SOC_OFFSET 0x1E000000 #define SPBA0_BASE_ADDR 0x70000000 #define AIPS1_BASE_ADDR 0x73F00000 #define AIPS2_BASE_ADDR 0x83F00000 @@ -34,7 +35,8 @@ #define NFC_BASE_ADDR_AXI 0xCFFF0000 #define CS1_BASE_ADDR 0xB8000000 #elif defined(CONFIG_MX53) -#define IPU_CTRL_BASE_ADDR 0x18000000 +#define IPU_SOC_BASE_ADDR 0x18000000 +#define IPU_SOC_OFFSET 0x06000000 #define SPBA0_BASE_ADDR 0x50000000 #define AIPS1_BASE_ADDR 0x53F00000 #define AIPS2_BASE_ADDR 0x63F00000 @@ -48,6 +50,8 @@ #error "CPU_TYPE not defined" #endif +#define IPU_CTRL_BASE_ADDR IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET + #define IRAM_SIZE 0x00020000 /* 128 KB */ /* diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 9964c20..93b195f 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -33,27 +33,27 @@ #define IPU_DISP0_BASE 0x00000000 #define IPU_MCU_T_DEFAULT 8 #define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) -#define IPU_CM_REG_BASE 0x1E000000 -#define IPU_STAT_REG_BASE 0x1E000200 -#define IPU_IDMAC_REG_BASE 0x1E008000 -#define IPU_ISP_REG_BASE 0x1E010000 -#define IPU_DP_REG_BASE 0x1E018000 -#define IPU_IC_REG_BASE 0x1E020000 -#define IPU_IRT_REG_BASE 0x1E028000 -#define IPU_CSI0_REG_BASE 0x1E030000 -#define IPU_CSI1_REG_BASE 0x1E038000 -#define IPU_DI0_REG_BASE 0x1E040000 -#define IPU_DI1_REG_BASE 0x1E048000 -#define IPU_SMFC_REG_BASE 0x1E050000 -#define IPU_DC_REG_BASE 0x1E058000 -#define IPU_DMFC_REG_BASE 0x1E060000 -#define IPU_CPMEM_REG_BASE 0x1F000000 -#define IPU_LUT_REG_BASE 0x1F020000 -#define IPU_SRM_REG_BASE 0x1F040000 -#define IPU_TPM_REG_BASE 0x1F060000 -#define IPU_DC_TMPL_REG_BASE 0x1F080000 -#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000 -#define IPU_VDI_REG_BASE 0x1E068000 +#define IPU_CM_REG_BASE 0x00000000 +#define IPU_STAT_REG_BASE 0x00000200 +#define IPU_IDMAC_REG_BASE 0x00008000 +#define IPU_ISP_REG_BASE 0x00010000 +#define IPU_DP_REG_BASE 0x00018000 +#define IPU_IC_REG_BASE 0x00020000 +#define IPU_IRT_REG_BASE 0x00028000 +#define IPU_CSI0_REG_BASE 0x00030000 +#define IPU_CSI1_REG_BASE 0x00038000 +#define IPU_DI0_REG_BASE 0x00040000 +#define IPU_DI1_REG_BASE 0x00048000 +#define IPU_SMFC_REG_BASE 0x00050000 +#define IPU_DC_REG_BASE 0x00058000 +#define IPU_DMFC_REG_BASE 0x00060000 +#define IPU_CPMEM_REG_BASE 0x01000000 +#define IPU_LUT_REG_BASE 0x01020000 +#define IPU_SRM_REG_BASE 0x01040000 +#define IPU_TPM_REG_BASE 0x01060000 +#define IPU_DC_TMPL_REG_BASE 0x01080000 +#define IPU_ISP_TBPR_REG_BASE 0x010C0000 +#define IPU_VDI_REG_BASE 0x00680000 extern u32 *ipu_dc_tmpl_reg;