From patchwork Mon May 14 17:32:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 159113 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A84B5B7040 for ; Tue, 15 May 2012 04:42:48 +1000 (EST) Received: from localhost ([::1]:45665 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STz97-0007bv-C2 for incoming@patchwork.ozlabs.org; Mon, 14 May 2012 13:33:21 -0400 Received: from eggs.gnu.org ([208.118.235.92]:41621) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STz8N-0005Qp-Kd for qemu-devel@nongnu.org; Mon, 14 May 2012 13:32:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1STz8D-0000dG-0f for qemu-devel@nongnu.org; Mon, 14 May 2012 13:32:35 -0400 Received: from cantor2.suse.de ([195.135.220.15]:49646 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STz8C-0000c8-NX for qemu-devel@nongnu.org; Mon, 14 May 2012 13:32:24 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 44A3690983; Mon, 14 May 2012 19:32:21 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Mon, 14 May 2012 19:32:00 +0200 Message-Id: <1337016729-12285-14-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1337016729-12285-1-git-send-email-afaerber@suse.de> References: <1337016729-12285-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: peter.maydell@linaro.org, Igor Mitsyanko , Mark Langsdorf , Evgeny Voevodin , Dmitry Solodkiy , Maksim Kozlov , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH qom-next 13/22] arm_boot: Pass ARMCPU to arm_boot_info::write_secondary_boot() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adapt exynos4210 and highbank accordingly. The parameter itself is unused. Signed-off-by: Andreas Färber --- hw/arm-misc.h | 2 +- hw/arm_boot.c | 6 +++--- hw/exynos4210.c | 2 +- hw/exynos4210.h | 2 +- hw/highbank.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 5302ee8..d877f80 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -50,7 +50,7 @@ struct arm_boot_info { * perform any necessary CPU reset handling and set the PC for the * secondary CPUs to point at this boot blob. */ - void (*write_secondary_boot)(CPUARMState *env, + void (*write_secondary_boot)(ARMCPU *cpu, const struct arm_boot_info *info); void (*secondary_cpu_reset_hook)(CPUARMState *env, const struct arm_boot_info *info); diff --git a/hw/arm_boot.c b/hw/arm_boot.c index eb2d176..4955f01 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -59,7 +59,7 @@ static uint32_t smpboot[] = { 0 /* bootreg: Boot register address is held here */ }; -static void default_write_secondary(CPUARMState *env, +static void default_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { int n; @@ -303,7 +303,7 @@ static void do_cpu_reset(void *opaque) void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info) { - ARMCPU *cpu; + ARMCPU *cpu = arm_env_get_cpu(env); int kernel_size; int initrd_size; int n; @@ -402,7 +402,7 @@ void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info) rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader), info->loader_start); if (info->nb_cpus > 1) { - info->write_secondary_boot(env, info); + info->write_secondary_boot(cpu, info); } } info->is_linux = is_linux; diff --git a/hw/exynos4210.c b/hw/exynos4210.c index afc4bdc..ae53837 100644 --- a/hw/exynos4210.c +++ b/hw/exynos4210.c @@ -65,7 +65,7 @@ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; -void exynos4210_write_secondary(CPUARMState *env, +void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { int n; diff --git a/hw/exynos4210.h b/hw/exynos4210.h index f7c7027..b520676 100644 --- a/hw/exynos4210.h +++ b/hw/exynos4210.h @@ -97,7 +97,7 @@ typedef struct Exynos4210State { MemoryRegion bootreg_mem; } Exynos4210State; -void exynos4210_write_secondary(CPUARMState *env, +void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info); Exynos4210State *exynos4210_init(MemoryRegion *system_mem, diff --git a/hw/highbank.c b/hw/highbank.c index 4d6d728..45ca1ad 100644 --- a/hw/highbank.c +++ b/hw/highbank.c @@ -36,7 +36,7 @@ /* Board init. */ -static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info) +static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { int n; uint32_t smpboot[] = {