From patchwork Sun May 13 15:16:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 158838 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id E15E8B6FDE for ; Mon, 14 May 2012 01:17:06 +1000 (EST) Comment: DKIM? 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(3): Ditto. (*andnot3): Ditto. (*andnottf3): Ditto. (*3): Ditto. (tf3): Ditto. Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline SVN. Uros. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 187435) +++ config/i386/sse.md (working copy) @@ -1600,29 +1600,46 @@ "TARGET_SSE" { static char buf[32]; - const char *insn; - const char *suffix - = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : ""; + const char *ops; + const char *suffix; + switch (get_attr_mode (insn)) + { + case MODE_V8SF: + case MODE_V4SF: + suffix = "ps"; + break; + default: + suffix = ""; + } + switch (which_alternative) { case 0: - insn = "andn%s\t{%%2, %%0|%%0, %%2}"; + ops = "andn%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), insn, suffix); + snprintf (buf, sizeof (buf), ops, suffix); return buf; } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex") - (set_attr "mode" "")]) + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "") + (match_test "TARGET_AVX") + (const_string "") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "")))]) (define_expand "3" [(set (match_operand:VF 0 "register_operand") @@ -1640,29 +1657,46 @@ "TARGET_SSE && ix86_binary_operator_ok (, mode, operands)" { static char buf[32]; - const char *insn; - const char *suffix - = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : ""; + const char *ops; + const char *suffix; + switch (get_attr_mode (insn)) + { + case MODE_V8SF: + case MODE_V4SF: + suffix = "ps"; + break; + default: + suffix = ""; + } + switch (which_alternative) { case 0: - insn = "%s\t{%%2, %%0|%%0, %%2}"; + ops = "%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - insn = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), insn, suffix); + snprintf (buf, sizeof (buf), ops, suffix); return buf; } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex") - (set_attr "mode" "")]) + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "") + (match_test "TARGET_AVX") + (const_string "") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "")))]) (define_expand "copysign3" [(set (match_dup 4) @@ -1696,30 +1730,85 @@ "SSE_FLOAT_MODE_P (mode)" { static char buf[32]; - const char *insn; + const char *ops; const char *suffix - = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : ""; + = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : ""; switch (which_alternative) { case 0: - insn = "andn%s\t{%%2, %%0|%%0, %%2}"; + ops = "andn%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - insn = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "vandn%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), insn, suffix); + snprintf (buf, sizeof (buf), ops, suffix); return buf; } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex") - (set_attr "mode" "")]) + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "")))]) +(define_insn "*andnottf3" + [(set (match_operand:TF 0 "register_operand" "=x,x") + (and:TF + (not:TF (match_operand:TF 1 "register_operand" "0,x")) + (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] + "TARGET_SSE" +{ + static char buf[32]; + const char *ops; + const char *tmp + = (get_attr_mode (insn) == MODE_V4SF) ? "andnps" : "pandn"; + + switch (which_alternative) + { + case 0: + ops = "%s\t{%%2, %%0|%%0, %%2}"; + break; + case 1: + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + break; + default: + gcc_unreachable (); + } + + snprintf (buf, sizeof (buf), ops, tmp); + return buf; +} + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") + (set (attr "prefix_data16") + (if_then_else + (and (eq_attr "alternative" "0") + (eq_attr "mode" "TI")) + (const_string "1") + (const_string "*"))) + (set_attr "prefix" "orig,vex") + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "TI") + (ior (not (match_test "TARGET_SSE2")) + (match_test "optimize_function_for_size_p (cfun)")) + (const_string "V4SF") + ] + (const_string "TI")))]) + (define_insn "*3" [(set (match_operand:MODEF 0 "register_operand" "=x,x") (any_logic:MODEF @@ -1728,30 +1817,94 @@ "SSE_FLOAT_MODE_P (mode)" { static char buf[32]; - const char *insn; + const char *ops; const char *suffix - = TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ? "ps" : ""; + = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : ""; switch (which_alternative) { case 0: - insn = "%s\t{%%2, %%0|%%0, %%2}"; + ops = "%s\t{%%2, %%0|%%0, %%2}"; break; case 1: - insn = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; break; default: gcc_unreachable (); } - snprintf (buf, sizeof (buf), insn, suffix); + snprintf (buf, sizeof (buf), ops, suffix); return buf; } [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex") - (set_attr "mode" "")]) + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "")))]) +(define_expand "tf3" + [(set (match_operand:TF 0 "register_operand") + (any_logic:TF + (match_operand:TF 1 "nonimmediate_operand") + (match_operand:TF 2 "nonimmediate_operand")))] + "TARGET_SSE" + "ix86_fixup_binary_operands_no_copy (, TFmode, operands);") + +(define_insn "*tf3" + [(set (match_operand:TF 0 "register_operand" "=x,x") + (any_logic:TF + (match_operand:TF 1 "nonimmediate_operand" "%0,x") + (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] + "TARGET_SSE + && ix86_binary_operator_ok (, TFmode, operands)" +{ + static char buf[32]; + const char *ops; + const char *tmp + = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "p"; + + switch (which_alternative) + { + case 0: + ops = "%s\t{%%2, %%0|%%0, %%2}"; + break; + case 1: + ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}"; + break; + default: + gcc_unreachable (); + } + + snprintf (buf, sizeof (buf), ops, tmp); + return buf; +} + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sselog") + (set (attr "prefix_data16") + (if_then_else + (and (eq_attr "alternative" "0") + (eq_attr "mode" "TI")) + (const_string "1") + (const_string "*"))) + (set_attr "prefix" "orig,vex") + (set (attr "mode") + (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "TI") + (ior (not (match_test "TARGET_SSE2")) + (match_test "optimize_function_for_size_p (cfun)")) + (const_string "V4SF") + ] + (const_string "TI")))]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; FMA4 floating point multiply/accumulate instructions. This @@ -6659,45 +6812,6 @@ ] (const_string "")))]) -(define_insn "*andnottf3" - [(set (match_operand:TF 0 "register_operand" "=x,x") - (and:TF - (not:TF (match_operand:TF 1 "register_operand" "0,x")) - (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] - "TARGET_SSE2" - "@ - pandn\t{%2, %0|%0, %2} - vpandn\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx") - (set_attr "type" "sselog") - (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") - (set_attr "mode" "TI")]) - -(define_expand "tf3" - [(set (match_operand:TF 0 "register_operand") - (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand") - (match_operand:TF 2 "nonimmediate_operand")))] - "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (, TFmode, operands);") - -(define_insn "*tf3" - [(set (match_operand:TF 0 "register_operand" "=x,x") - (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand" "%0,x") - (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] - "TARGET_SSE2 - && ix86_binary_operator_ok (, TFmode, operands)" - "@ - p\t{%2, %0|%0, %2} - vp\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx") - (set_attr "type" "sselog") - (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") - (set_attr "mode" "TI")]) - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral element swizzling