Patchwork [U-Boot,2/2] MSM7x27a:Add support for USB gadget

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Submitter srikanth.reddy@lntinfotech.com
Date May 11, 2012, 6:54 a.m.
Message ID <1336719262-24057-3-git-send-email-srikanth.reddy@lntinfotech.com>
Download mbox | patch
Permalink /patch/158442/
State Rejected
Delegated to: Marek Vasut
Headers show

Comments

srikanth.reddy@lntinfotech.com - May 11, 2012, 6:54 a.m.
* USB gadget support

Signed-off-by: Srikanth Reddy Vintha <srikanth.reddy@lntinfotech.com>
---
 arch/arm/cpu/armv7/msm7x27a/acpuclock.c    |    7 +
 arch/arm/include/asm/arch-msm7x27a/hsusb.h |  183 ++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-msm7x27a/iomap.h |    2 +
 drivers/usb/gadget/msm_udc.c               |   11 +-
 include/configs/msm7x27a_surf.h            |   12 +-
 5 files changed, 205 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-msm7x27a/hsusb.h

Patch

diff --git a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
index 7f46d18..ae9db0d 100644
--- a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
+++ b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c
@@ -220,6 +220,13 @@  void acpu_clock_init(void)
 	}
 }
 
+void hsusb_clock_init(void)
+{
+	/* USB local clock control not enabled; use proc comm */
+	usb_clock_init();
+}
+
+
 #ifdef CONFIG_QC_MMC
 /* Configure MMC clock */
 void clock_config_mmc(uint32_t interface, uint32_t freq)
diff --git a/arch/arm/include/asm/arch-msm7x27a/hsusb.h b/arch/arm/include/asm/arch-msm7x27a/hsusb.h
new file mode 100644
index 0000000..0a8f853
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7x27a/hsusb.h
@@ -0,0 +1,183 @@ 
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _HSUSB_H_
+#define _HSUSB_H_
+
+#include <asm/arch/iomap.h>
+
+#ifndef MSM_USB_BASE
+#error Must define base address for USB controller MSM_USB_BASE
+#endif
+
+#define USB_ID               (MSM_USB_BASE + 0x0000)
+#define USB_HWGENERAL        (MSM_USB_BASE + 0x0004)
+#define USB_HWHOST           (MSM_USB_BASE + 0x0008)
+#define USB_HWDEVICE         (MSM_USB_BASE + 0x000C)
+#define USB_HWTXBUF          (MSM_USB_BASE + 0x0010)
+#define USB_HWRXBUF          (MSM_USB_BASE + 0x0014)
+#define USB_SBUSCFG          (MSM_USB_BASE + 0x0090)
+
+#define USB_AHB_BURST        (MSM_USB_BASE + 0x0090)
+#define USB_AHB_MODE         (MSM_USB_BASE + 0x0098)
+#define USB_CAPLENGTH        (MSM_USB_BASE + 0x0100) /* 8 bit */
+#define USB_HCIVERSION       (MSM_USB_BASE + 0x0102) /* 16 bit */
+#define USB_HCSPARAMS        (MSM_USB_BASE + 0x0104)
+#define USB_HCCPARAMS        (MSM_USB_BASE + 0x0108)
+#define USB_DCIVERSION       (MSM_USB_BASE + 0x0120) /* 16 bit */
+#define USB_USBCMD           (MSM_USB_BASE + 0x0140)
+#define USB_USBSTS           (MSM_USB_BASE + 0x0144)
+#define USB_USBINTR          (MSM_USB_BASE + 0x0148)
+#define USB_FRINDEX          (MSM_USB_BASE + 0x014C)
+#define USB_DEVICEADDR       (MSM_USB_BASE + 0x0154)
+#define USB_ENDPOINTLISTADDR (MSM_USB_BASE + 0x0158)
+#define USB_BURSTSIZE        (MSM_USB_BASE + 0x0160)
+#define USB_TXFILLTUNING     (MSM_USB_BASE + 0x0164)
+#define USB_ULPI_VIEWPORT    (MSM_USB_BASE + 0x0170)
+#define USB_ENDPTNAK         (MSM_USB_BASE + 0x0178)
+#define USB_ENDPTNAKEN       (MSM_USB_BASE + 0x017C)
+#define USB_PORTSC           (MSM_USB_BASE + 0x0184)
+#define USB_OTGSC            (MSM_USB_BASE + 0x01A4)
+#define USB_USBMODE          (MSM_USB_BASE + 0x01A8)
+#define USB_ENDPTSETUPSTAT   (MSM_USB_BASE + 0x01AC)
+#define USB_ENDPTPRIME       (MSM_USB_BASE + 0x01B0)
+#define USB_ENDPTFLUSH       (MSM_USB_BASE + 0x01B4)
+#define USB_ENDPTSTAT        (MSM_USB_BASE + 0x01B8)
+#define USB_ENDPTCOMPLETE    (MSM_USB_BASE + 0x01BC)
+#define USB_ENDPTCTRL(n)     (MSM_USB_BASE + 0x01C0 + (4 * (n)))
+
+
+#define USBCMD_RESET   2
+#define USBCMD_ATTACH  1
+
+#define USBMODE_DEVICE 2
+#define USBMODE_HOST   3
+
+/* Endpoint Txfer Descriptor dTD as defined by DC */
+struct ept_queue_item {
+	struct ept_queue_item *next;
+#define UDC_DTD_TOTAL_BYTES(info) (((info) >> 16) & 0x7FFF)
+	unsigned info; /* 30:16-Total Bytes,7:0-Status */
+	unsigned page0;
+	unsigned page1;
+	unsigned page2;
+	unsigned page3;
+	unsigned page4;
+	unsigned reserved;
+	};
+
+/* Endpoint Queue Head (dQH) as defined by the DC must take up 64K.
+ * There must be one dQH for every endpoint and direction. */
+struct ept_queue_head {
+	unsigned config;
+	unsigned current; /* read-only */
+	unsigned next;
+	unsigned info;
+	unsigned page0;
+	unsigned page1;
+	unsigned page2;
+	unsigned page3;
+	unsigned page4;
+	unsigned reserved_0;
+	unsigned char setup_data[8];
+	unsigned reserved_1;
+	unsigned reserved_2;
+	unsigned reserved_3;
+	unsigned reserved_4;
+};
+
+#define CONFIG_MAX_PKT(n)     ((n) << 16)
+#define CONFIG_ZLT            (1 << 29)    /* stop on zero-len xfer */
+#define CONFIG_IOS            (1 << 15)    /* IRQ on setup */
+
+
+#define TERMINATE 1
+
+#define INFO_BYTES(n)         ((n) << 16)
+#define INFO_IOC              (1 << 15)
+#define INFO_ACTIVE           (1 << 7)
+#define INFO_HALTED           (1 << 6)
+#define INFO_BUFFER_ERROR     (1 << 5)
+#define INFO_TX_ERROR         (1 << 3)
+
+
+#define STS_NAKI        (1 << 16)  /* */
+#define STS_SLI         (1 << 8)   /* R/WC - suspend state entered */
+#define STS_SRI         (1 << 7)   /* R/WC - SOF recv'd */
+#define STS_URI		(1 << 6)   /* R/WC - RESET recv'd - write to clear */
+#define STS_FRI         (1 << 3)   /* R/WC - Frame List Rollover */
+#define STS_PCI         (1 << 2)   /* R/WC - Port Change Detect */
+#define STS_UEI         (1 << 1)   /* R/WC - USB Error Interrupt*/
+#define STS_UI          (1 << 0)   /* R/WC - USB Interrupt Trans Complete */
+
+/* bits used in all the endpoint status registers */
+#define EPT_TX(n) (1 << ((n) + 16))
+#define EPT_RX(n) (1 << (n))
+
+
+#define CTRL_TXE              (1 << 23) /* TX Endpoint Enable */
+#define CTRL_TXR              (1 << 22) /* TX Data Toggle Reset */
+#define CTRL_TXI              (1 << 21) /* TX Data Toggle Inhibit */
+#define CTRL_TXT(n)           ((n) << 18) /* TX Endpoint Type */
+#define CTRL_TXD              (1 << 17) /* TX Endpoint Data Source */
+#define CTRL_TXS              (1 << 16) /* TX Endpoint Stall */
+#define CTRL_RXE              (1 << 7) /* RX Endpoint Enable */
+#define CTRL_RXR              (1 << 6) /* RX Data Toggle Reset */
+#define CTRL_RXI              (1 << 5) /* RX Data Toggle Inhibit */
+#define CTRL_RXT(n)           ((n) << 2) /* RX Endpoint Type */
+#define CTRL_RXD              (1 << 1) /* RX Endpoint Data Source */
+#define CTRL_RXS              (1 << 0) /* RX Endpint Stall */
+
+#define CTRL_TXT_CTRL         (0 << 18)
+#define CTRL_TXT_ISOCH        (1 << 18)
+#define CTRL_TXT_BULK         (2 << 18)
+#define CTRL_TXT_INT          (3 << 18)
+
+#define CTRL_RXT_CTRL         (0 << 2)
+#define CTRL_RXT_ISOCH        (1 << 2)
+#define CTRL_RXT_BULK         (2 << 2)
+#define CTRL_RXT_INT          (3 << 2)
+
+#define ULPI_WAKEUP           (1 << 31)
+#define ULPI_RUN              (1 << 30)
+#define ULPI_WRITE            (1 << 29)
+#define ULPI_READ             (0 << 29)
+#define ULPI_STATE_NORMAL     (1 << 27)
+#define ULPI_ADDR(n)          (((n) & 255) << 16)
+#define ULPI_DATA(n)          ((n) & 255)
+#define ULPI_DATA_READ(n)     (((n) >> 8) & 255)
+
+#define PORTSC_PTC           (0xF << 16)
+#define PORTSC_PTC_TST_PKT   (0x4 << 16)
+
+#endif
diff --git a/arch/arm/include/asm/arch-msm7x27a/iomap.h b/arch/arm/include/asm/arch-msm7x27a/iomap.h
index 4c9d434..adc0b02 100644
--- a/arch/arm/include/asm/arch-msm7x27a/iomap.h
+++ b/arch/arm/include/asm/arch-msm7x27a/iomap.h
@@ -48,6 +48,8 @@ 
 
 #define MSM_SHARED_BASE 0x00100000
 
+#define MSM_USB_BASE 0xA0800000
+
 #define MSM_SDC1_BASE   0xA0400000
 #define MSM_SDC3_BASE   0xA0600000
 
diff --git a/drivers/usb/gadget/msm_udc.c b/drivers/usb/gadget/msm_udc.c
index 7c2a14a..1fbbbfb 100644
--- a/drivers/usb/gadget/msm_udc.c
+++ b/drivers/usb/gadget/msm_udc.c
@@ -173,8 +173,10 @@  static void msm_udc_handle_setup(void)
 		udcdbg("clear feature\n");
 		if ((s.wValue == 0) && (s.wLength == 0)) {
 			unsigned num = s.wIndex & USB_ENDPOINT_NUMBER_MASK;
-			unsigned direction = s.wIndex & USB_ENDPOINT_DIR_MASK;
-
+			#ifdef DEBUG
+				unsigned direction =
+					 s.wIndex & USB_ENDPOINT_DIR_MASK;
+			#endif
 			udcdbg("Clear feature ep%i%s\n", num, direction ?
 				"in" : "out");
 			msm_udc_ep_enable(num, 1);
@@ -217,7 +219,7 @@  static void msm_udc_handle_setup(void)
 
 static void msm_udc_ep_complete(unsigned num, unsigned direction)
 {
-	struct ept_queue_item *dTD = dTD_list[num];
+	struct ept_queue_item *dTD = (struct ept_queue_item *) dTD_list[num];
 	struct usb_endpoint_instance *epi =
 		&udc_device->bus->endpoint_array[num];
 	struct urb *urb = msm_udc_get_urb_by_dir(num, direction);
@@ -383,7 +385,8 @@  int udc_endpoint_write(struct usb_endpoint_instance *epi)
 	enter_critical_section();
 	/* Handle the case where there are completed dTDs waiting */
 	if (dTD_list[num] != NULL) {
-		struct ept_queue_item *dTDlast = dTD_list[num];
+		struct ept_queue_item *dTDlast =
+				(struct ept_queue_item *)dTD_list[num];
 		unsigned qDepth = 1;
 		while (dTDlast->next != (struct ept_queue_item *) TERMINATE) {
 			dTDlast = dTDlast->next;
diff --git a/include/configs/msm7x27a_surf.h b/include/configs/msm7x27a_surf.h
index 2b5efb8..5f0eed3 100644
--- a/include/configs/msm7x27a_surf.h
+++ b/include/configs/msm7x27a_surf.h
@@ -38,6 +38,11 @@ 
  */
 #define CONFIG_SYS_MALLOC_LEN           (2 * 1024)	/* 2KB  */
 
+/* Enable USB */
+#define CONFIG_MSM_UDC
+#define CONFIG_USB_TTY
+#define CONFIG_USB_DEVICE
+
 /*
  * select serial console configuration
  */
@@ -60,7 +65,7 @@ 
 #undef CONFIG_CMD_NET		/* network support */
 #undef CONFIG_SYS_MAX_FLASH_SECT
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"console=ttyS0,115200n8\0" \
+	"usbtty=cdc_acm\0"
 
 #define CONFIG_BOOTDELAY	-1
 
@@ -106,10 +111,6 @@ 
  * Physical Memory Map
  */
 
-#if 0
-#define CONFIG_BOOTDELAY       0
-#define CONFIG_BOOTCOMMAND		"mmc part"
-#endif
 #define CONFIG_NR_DRAM_BANKS		1
 
 #define PHYS_SDRAM_1			0x00000000
@@ -124,5 +125,4 @@ 
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 						CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
-
 #endif