Patchwork [U-Boot,1/3] MSM7630 Interrupt support

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Submitter mohamed.haneef@lntinfotech.com
Date May 11, 2012, 6:04 a.m.
Message ID <1336716299-23611-2-git-send-email-mohamed.haneef@lntinfotech.com>
Download mbox | patch
Permalink /patch/158431/
State Changes Requested
Delegated to: Albert ARIBAUD
Headers show

Comments

mohamed.haneef@lntinfotech.com - May 11, 2012, 6:04 a.m.
* Support for msm7630 interrupts

Signed-off-by: Mohamed Haneef <mohamed.haneef@lntinfotech.com>
---
 arch/arm/cpu/armv7/msm7630/Makefile            |    1 +
 arch/arm/cpu/armv7/msm7630/interrupts.c        |  155 +++++++++++++++++++++
 arch/arm/include/asm/arch-msm7630/exclusion.h  |   42 ++++++
 arch/arm/include/asm/arch-msm7630/interrupts.h |   40 ++++++
 arch/arm/include/asm/arch-msm7630/irqs.h       |  173 ++++++++++++++++++++++++
 board/qcom/msm7630_surf/msm7630_surf.c         |    3 +
 6 files changed, 414 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/msm7630/interrupts.c
 create mode 100644 arch/arm/include/asm/arch-msm7630/exclusion.h
 create mode 100644 arch/arm/include/asm/arch-msm7630/interrupts.h
 create mode 100644 arch/arm/include/asm/arch-msm7630/irqs.h
Marek Vasut - May 12, 2012, 6:22 a.m.
Dear Mohamed Haneef,

> 	* Support for msm7630 interrupts
> 
> Signed-off-by: Mohamed Haneef <mohamed.haneef@lntinfotech.com>
> ---
>  arch/arm/cpu/armv7/msm7630/Makefile            |    1 +
>  arch/arm/cpu/armv7/msm7630/interrupts.c        |  155
> +++++++++++++++++++++ arch/arm/include/asm/arch-msm7630/exclusion.h  |  
> 42 ++++++
>  arch/arm/include/asm/arch-msm7630/interrupts.h |   40 ++++++
>  arch/arm/include/asm/arch-msm7630/irqs.h       |  173
> ++++++++++++++++++++++++ board/qcom/msm7630_surf/msm7630_surf.c         | 
>   3 +

I dont see this file in the tree ... home come? Does this patch depend on some 
other patchset?

>  6 files changed, 414 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/msm7630/interrupts.c
>  create mode 100644 arch/arm/include/asm/arch-msm7630/exclusion.h
>  create mode 100644 arch/arm/include/asm/arch-msm7630/interrupts.h
>  create mode 100644 arch/arm/include/asm/arch-msm7630/irqs.h
> 
> diff --git a/arch/arm/cpu/armv7/msm7630/Makefile
> b/arch/arm/cpu/armv7/msm7630/Makefile index b97026f..b106ddc 100644
> --- a/arch/arm/cpu/armv7/msm7630/Makefile
> +++ b/arch/arm/cpu/armv7/msm7630/Makefile
> @@ -40,6 +40,7 @@ COBJS-y		:= board.o
>  COBJS-y		+= timer.o
>  COBJS-y		+= acpuclock.o
>  COBJS-y		+= gpio.o
> +COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
> 
>   SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
>   OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
> diff --git a/arch/arm/cpu/armv7/msm7630/interrupts.c
> b/arch/arm/cpu/armv7/msm7630/interrupts.c new file mode 100644
> index 0000000..6cae9c8
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/msm7630/interrupts.c
> @@ -0,0 +1,155 @@
> +/*
> + * Copyright (c) 2008, Google Inc.
> + * All rights reserved.
> + *
> + * (C) Copyright 2012
> + * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + *  * Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer.
> + *  * Redistributions in binary form must reproduce the above copyright
> + *    notice, this list of conditions and the following disclaimer in
> + *    the documentation and/or other materials provided with the
> + *    distribution.
> + *  * Neither the name of Google, Inc. nor the names of its contributors
> + *    may be used to endorse or promote products derived from this
> + *    software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
> + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
> + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
> + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
> + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
> + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
> + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
> + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
> + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.

DTTO, see my previous response. I'm not sure if we can accept code that's not 
GPL. Let's see.

Patch

diff --git a/arch/arm/cpu/armv7/msm7630/Makefile b/arch/arm/cpu/armv7/msm7630/Makefile
index b97026f..b106ddc 100644
--- a/arch/arm/cpu/armv7/msm7630/Makefile
+++ b/arch/arm/cpu/armv7/msm7630/Makefile
@@ -40,6 +40,7 @@  COBJS-y		:= board.o
 COBJS-y		+= timer.o
 COBJS-y		+= acpuclock.o
 COBJS-y		+= gpio.o
+COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
 
  SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
  OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
diff --git a/arch/arm/cpu/armv7/msm7630/interrupts.c b/arch/arm/cpu/armv7/msm7630/interrupts.c
new file mode 100644
index 0000000..6cae9c8
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7630/interrupts.c
@@ -0,0 +1,155 @@ 
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of Google, Inc. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/interrupts.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/exclusion.h>
+
+#define VIC_REG(off) (MSM_VIC_BASE + (off))
+
+#define VIC_INT_SELECT0     VIC_REG(0x0000)	/* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1     VIC_REG(0x0004)	/* 1: FIQ, 0: IRQ */
+#define VIC_INT_EN0         VIC_REG(0x0010)
+#define VIC_INT_EN1         VIC_REG(0x0014)
+#define VIC_INT_ENCLEAR0    VIC_REG(0x0020)
+#define VIC_INT_ENCLEAR1    VIC_REG(0x0024)
+#define VIC_INT_ENSET0      VIC_REG(0x0030)
+#define VIC_INT_ENSET1      VIC_REG(0x0034)
+#define VIC_INT_TYPE0       VIC_REG(0x0040)	/* 1: EDGE, 0: LEVEL  */
+#define VIC_INT_TYPE1       VIC_REG(0x0044)	/* 1: EDGE, 0: LEVEL  */
+#define VIC_INT_POLARITY0   VIC_REG(0x0050)	/* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY1   VIC_REG(0x0054)	/* 1: NEG, 0: POS */
+#define VIC_NO_PEND_VAL     VIC_REG(0x0060)
+#define VIC_INT_MASTEREN    VIC_REG(0x0068)	/* 1: IRQ, 2: FIQ     */
+#define VIC_CONFIG          VIC_REG(0x006C)	/* 1: USE ARM1136 VIC */
+#define VIC_SECURITY0       VIC_REG(0x0070)
+#define VIC_SECURITY1       VIC_REG(0x0074)
+#define VIC_IRQ_STATUS0     VIC_REG(0x0080)
+#define VIC_IRQ_STATUS1     VIC_REG(0x0084)
+#define VIC_FIQ_STATUS0     VIC_REG(0x0090)
+#define VIC_FIQ_STATUS1     VIC_REG(0x0094)
+#define VIC_RAW_STATUS0     VIC_REG(0x00A0)
+#define VIC_RAW_STATUS1     VIC_REG(0x00A4)
+#define VIC_INT_CLEAR0      VIC_REG(0x00B0)
+#define VIC_INT_CLEAR1      VIC_REG(0x00B4)
+#define VIC_SOFTINT0        VIC_REG(0x00C0)
+#define VIC_SOFTINT1        VIC_REG(0x00C4)
+#define VIC_IRQ_VEC_RD      VIC_REG(0x00D0)	/* pending int # */
+#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4)	/* pending vector addr */
+#define VIC_IRQ_VEC_WR      VIC_REG(0x00D8)
+#define VIC_FIQ_VEC_RD      VIC_REG(0x00DC)	/* pending int # */
+#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0)	/* pending vector addr */
+#define VIC_FIQ_VEC_WR      VIC_REG(0x00E4)
+#define VIC_IRQ_IN_SERVICE  VIC_REG(0x00E8)
+#define VIC_IRQ_IN_STACK    VIC_REG(0x00EC)
+#define VIC_FIQ_IN_SERVICE  VIC_REG(0x00F0)
+#define VIC_FIQ_IN_STACK    VIC_REG(0x00F4)
+#define VIC_TEST_BUS_SEL    VIC_REG(0x00F8)
+
+#define SIRC_REG(off) (MSM_SIRC_BASE + (off))
+
+#define SIRC_INT_SELECT     SIRC_REG(0x0000)	/* 0: IRQ0 1: IRQ1 */
+#define SIRC_INT_ENABLE     SIRC_REG(0x0004)
+#define SIRC_INT_ENCLEAR    SIRC_REG(0x0008)
+#define SIRC_INT_ENSET      SIRC_REG(0x000C)
+#define SIRC_INT_TYPE       SIRC_REG(0x0010)	/* 1: EDGE, 0: LEVEL */
+#define SIRC_INT_POLARITY   SIRC_REG(0x0014)	/* 1: NEG, 0: POS */
+#define SIRC_SECURITY       SIRC_REG(0x0018)	/* 0: SEC, 1: NSEC */
+#define SIRC_IRQ0_STATUS    SIRC_REG(0x001C)
+#define SIRC_IRQ1_STATUS    SIRC_REG(0x0020)
+#define SIRC_RAW_STATUS     SIRC_REG(0x0024)
+
+struct ihandler {
+	int_handler func;
+	void *arg;
+};
+
+static struct ihandler handler[NR_IRQS];
+
+int  arch_interrupt_init(void)
+{
+	writel(0xffffffff, VIC_INT_CLEAR0);
+	writel(0xffffffff, VIC_INT_CLEAR1);
+	writel(0, VIC_INT_SELECT0);
+	writel(0, VIC_INT_SELECT1);
+	writel(0xffffffff, VIC_INT_TYPE0);
+	writel(0xffffffff, VIC_INT_TYPE1);
+	writel(0, VIC_CONFIG);
+	writel(1, VIC_INT_MASTEREN);
+	return 0;
+}
+
+void do_irq(struct pt_regs *pt_regs)
+{
+	unsigned num;
+	enum handler_return ret;
+	num = readl(VIC_IRQ_VEC_RD);
+	num = readl(VIC_IRQ_VEC_PEND_RD);
+	if (num > NR_IRQS)
+		return;
+	(void) handler[num].func(handler[num].arg);
+	writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
+	writel(0, VIC_IRQ_VEC_WR);
+}
+
+int mask_interrupt(unsigned int vector)
+{
+	unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
+	unsigned bit = 1 << (vector & 31);
+	writel(bit, reg);
+	return 0;
+}
+
+int unmask_interrupt(unsigned int vector)
+{
+	unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
+	unsigned bit = 1 << (vector & 31);
+	writel(bit, reg);
+	return 0;
+}
+
+void register_int_handler(unsigned int vector, int_handler func, void *arg)
+{
+	if (vector >= NR_IRQS) {
+		debug("could not set interrupt %#08x", vector);
+		return;
+	}
+	enter_critical_section();
+	handler[vector].func = func;
+	handler[vector].arg = arg;
+	exit_critical_section();
+}
diff --git a/arch/arm/include/asm/arch-msm7630/exclusion.h b/arch/arm/include/asm/arch-msm7630/exclusion.h
new file mode 100644
index 0000000..e98716e
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/exclusion.h
@@ -0,0 +1,42 @@ 
+/*
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __EXCLUSION_H
+#define __EXCLUSION_H
+#include <common.h>
+
+/* critical sections */
+extern int critical_section_count;
+
+static inline __attribute__((always_inline)) void enter_critical_section(void)
+{
+	critical_section_count++;
+	if (critical_section_count == 1)
+		disable_interrupts();
+}
+
+static inline __attribute__((always_inline)) void exit_critical_section(void)
+{
+	critical_section_count--;
+	if (critical_section_count == 0)
+		enable_interrupts();
+}
+
+#endif
diff --git a/arch/arm/include/asm/arch-msm7630/interrupts.h b/arch/arm/include/asm/arch-msm7630/interrupts.h
new file mode 100644
index 0000000..e7b95de
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/interrupts.h
@@ -0,0 +1,40 @@ 
+/*
+ * Copyright (c) 2008 Travis Geiselbrecht
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __PLATFORM_INTERRUPTS_H
+#define __PLATFORM_INTERRUPTS_H
+
+enum handler_return {
+	INT_NO_RESCHEDULE = 0,
+	INT_RESCHEDULE,
+};
+
+
+typedef enum handler_return (*int_handler)(void *arg);
+
+void register_int_handler(unsigned int vector, int_handler handler, void *arg);
+int mask_interrupt(unsigned int vector);
+int unmask_interrupt(unsigned int vector);
+#endif
diff --git a/arch/arm/include/asm/arch-msm7630/irqs.h b/arch/arm/include/asm/arch-msm7630/irqs.h
new file mode 100644
index 0000000..2310e3e
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/irqs.h
@@ -0,0 +1,173 @@ 
+/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ *
+ * (C) Copyright 2012
+ * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_7X30_H
+#define __ASM_ARCH_MSM_IRQS_7X30_H
+
+/* MSM ACPU Interrupt Numbers */
+
+#define INT_DEBUG_TIMER_EXP	0
+#define INT_GPT0_TIMER_EXP	1
+#define INT_GPT1_TIMER_EXP	2
+#define INT_WDT0_ACCSCSSBARK	3
+#define INT_WDT1_ACCSCSSBARK	4
+#define INT_AVS_SVIC		5
+#define INT_AVS_SVIC_SW_DONE	6
+#define INT_SC_DBG_RX_FULL	7
+#define INT_SC_DBG_TX_EMPTY	8
+#define INT_SC_PERF_MON		9
+#define INT_AVS_REQ_DOWN	10
+#define INT_AVS_REQ_UP		11
+#define INT_SC_ACG		12
+/* SCSS_VICFIQSTS1[13:15] are RESERVED */
+#define INT_L2_SVICCPUIRPTREQ	16
+#define INT_L2_SVICDMANSIRPTREQ 17
+#define INT_L2_SVICDMASIRPTREQ  18
+#define INT_L2_SVICSLVIRPTREQ	19
+#define INT_AD5A_MPROC_APPS_0	20
+#define INT_AD5A_MPROC_APPS_1	21
+#define INT_A9_M2A_0		22
+#define INT_A9_M2A_1		23
+#define INT_A9_M2A_2		24
+#define INT_A9_M2A_3		25
+#define INT_A9_M2A_4		26
+#define INT_A9_M2A_5		27
+#define INT_A9_M2A_6		28
+#define INT_A9_M2A_7		29
+#define INT_A9_M2A_8		30
+#define INT_A9_M2A_9		31
+
+#define INT_AXI_EBI1_SC		(32 + 0)
+#define INT_IMEM_ERR		(32 + 1)
+#define INT_AXI_EBI0_SC		(32 + 2)
+#define INT_PBUS_SC_IRQC	(32 + 3)
+#define INT_PERPH_BUS_BPM	(32 + 4)
+#define INT_CC_TEMP_SENSE	(32 + 5)
+#define INT_UXMC_EBI0		(32 + 6)
+#define INT_UXMC_EBI1		(32 + 7)
+#define INT_EBI2_OP_DONE	(32 + 8)
+#define INT_EBI2_WR_ER_DONE	(32 + 9)
+#define INT_TCSR_SPSS_CE	(32 + 10)
+#define INT_EMDH		(32 + 11)
+#define INT_PMDH		(32 + 12)
+#define INT_MDC			(32 + 13)
+#define INT_MIDI_TO_SUPSS	(32 + 14)
+#define INT_LPA_2		(32 + 15)
+#define INT_GPIO_GROUP1_SECURE	(32 + 16)
+#define INT_GPIO_GROUP2_SECURE	(32 + 17)
+#define INT_GPIO_GROUP1		(32 + 18)
+#define INT_GPIO_GROUP2		(32 + 19)
+#define INT_MPRPH_SOFTRESET	(32 + 20)
+#define INT_PWB_I2C		(32 + 21)
+#define INT_PWB_I2C_2		(32 + 22)
+#define INT_TSSC_SAMPLE		(32 + 23)
+#define INT_TSSC_PENUP		(32 + 24)
+#define INT_TCHSCRN_SSBI	(32 + 25)
+#define INT_FM_RDS		(32 + 26)
+#define INT_KEYSENSE		(32 + 27)
+#define INT_USB_OTG_HS		(32 + 28)
+#define INT_USB_OTG_HS2		(32 + 29)
+#define INT_USB_OTG_HS3		(32 + 30)
+#define INT_RESERVED_BIT31	(32 + 31)
+
+#define INT_SPI_OUTPUT		(64 + 0)
+#define INT_SPI_INPUT		(64 + 1)
+#define INT_SPI_ERROR		(64 + 2)
+#define INT_UART1		(64 + 3)
+#define INT_UART1_RX		(64 + 4)
+#define INT_UART2		(64 + 5)
+#define INT_UART2_RX		(64 + 6)
+#define INT_UART3		(64 + 7)
+#define INT_UART3_RX		(64 + 8)
+#define INT_UART1DM_IRQ		(64 + 9)
+#define INT_UART1DM_RX		(64 + 10)
+#define INT_UART2DM_IRQ		(64 + 11)
+#define INT_UART2DM_RX		(64 + 12)
+#define INT_TSIF		(64 + 13)
+#define INT_ADM_SC1		(64 + 14)
+#define INT_ADM_SC2		(64 + 15)
+#define INT_MDP			(64 + 16)
+#define INT_VPE			(64 + 17)
+#define INT_GRP_2D		(64 + 18)
+#define INT_GRP_3D		(64 + 19)
+#define INT_ROTATOR		(64 + 20)
+#define INT_MFC720		(64 + 21)
+#define INT_JPEG		(64 + 22)
+#define INT_VFE			(64 + 23)
+#define INT_TV_ENC		(64 + 24)
+#define INT_PMIC_SSBI		(64 + 25)
+#define INT_MPM_1		(64 + 26)
+#define INT_TCSR_SPSS_SAMPLE	(64 + 27)
+#define INT_TCSR_SPSS_PENUP	(64 + 28)
+#define INT_MPM_2		(64 + 29)
+#define INT_SDC1_0		(64 + 30)
+#define INT_SDC1_1		(64 + 31)
+
+#define INT_SDC3_0		(96 + 0)
+#define INT_SDC3_1		(96 + 1)
+#define INT_SDC2_0		(96 + 2)
+#define INT_SDC2_1		(96 + 3)
+#define INT_SDC4_0		(96 + 4)
+#define INT_SDC4_1		(96 + 5)
+#define INT_PWB_QUP_IN		(96 + 6)
+#define INT_PWB_QUP_OUT		(96 + 7)
+#define INT_PWB_QUP_ERR		(96 + 8)
+/* SCSS_VICFIQSTS3[6:31] are RESERVED */
+
+/* Retrofit universal macro names */
+#define INT_ADM_AARM		INT_ADM_SC2
+#define INT_USB_HS		INT_USB_OTG_HS
+#define INT_USB_OTG		INT_USB_OTG_HS
+#define INT_TCHSCRN1		INT_TSSC_SAMPLE
+#define INT_TCHSCRN2		INT_TSSC_PENUP
+#define INT_GP_TIMER_EXP	INT_GPT0_TIMER_EXP
+#define INT_ADSP_A11		INT_AD5A_MPROC_APPS_0
+#define INT_ADSP_A9_A11		INT_AD5A_MPROC_APPS_1
+#define INT_MDDI_EXT		INT_EMDH
+#define INT_MDDI_PRI		INT_PMDH
+#define INT_MDDI_CLIENT		INT_MDC
+#define INT_NAND_WR_ER_DONE	INT_EBI2_WR_ER_DONE
+#define INT_NAND_OP_DONE	INT_EBI2_OP_DONE
+
+#define NR_MSM_IRQS		128
+#define NR_GPIO_IRQS		182
+#define PMIC8058_IRQ_BASE	(NR_MSM_IRQS + NR_GPIO_IRQS)
+#define NR_PMIC8058_GPIO_IRQS	40
+#define NR_PMIC8058_MPP_IRQS	12
+#define NR_PMIC8058_MISC_IRQS	8
+#define NR_PMIC8058_IRQS	(NR_PMIC8058_GPIO_IRQS +\
+				NR_PMIC8058_MPP_IRQS +\
+				NR_PMIC8058_MISC_IRQS)
+#define NR_BOARD_IRQS		NR_PMIC8058_IRQS
+
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
+
+#endif	/* __ASM_ARCH_MSM_IRQS_7X30_H */
diff --git a/board/qcom/msm7630_surf/msm7630_surf.c b/board/qcom/msm7630_surf/msm7630_surf.c
index 95c9f04..9dcf95b 100644
--- a/board/qcom/msm7630_surf/msm7630_surf.c
+++ b/board/qcom/msm7630_surf/msm7630_surf.c
@@ -30,6 +30,8 @@ 
 #include <asm/arch/proc_comm.h>
 #include "msm7630_surf.h"
 
+int critical_section_count;
+
 static struct msm_gpio uart2_gpio_table[] = {
 	{
 	.gpio_cfg = GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA),
@@ -61,6 +63,7 @@  void uart2_mux_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f()
 {
+	critical_section_count = 0;
 	uart2_mux_init();
 	uart2_clock_init();
 	return 0;