From patchwork Thu May 10 00:14:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 158090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2F485B6FB7 for ; Thu, 10 May 2012 11:03:14 +1000 (EST) Received: from localhost ([::1]:50566 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSH51-0005UA-PJ for incoming@patchwork.ozlabs.org; Wed, 09 May 2012 20:18:03 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50520) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSH2O-0001HW-5r for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SSH2L-0005b4-CW for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:19 -0400 Received: from cantor2.suse.de ([195.135.220.15]:35588 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSH2L-0005aG-1o for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:17 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 00DD5977E6; Thu, 10 May 2012 02:15:16 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Thu, 10 May 2012 02:14:19 +0200 Message-Id: <1336608892-30501-42-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1336608892-30501-1-git-send-email-afaerber@suse.de> References: <1336608892-30501-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Michael Walle , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH next v2 41/74] target-lm32: Let cpu_lm32_init() return LM32CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make the include paths for cpu-qom.h consistent to allow using LM32CPU in cpu.h. Turn cpu_init macro into a static inline function returning CPULM32State for backwards compatibility. Signed-off-by: Andreas Färber Acked-by: Michael Walle --- target-lm32/cpu.c | 2 +- target-lm32/cpu.h | 12 ++++++++++-- target-lm32/helper.c | 4 ++-- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 48a5fe3..caa4834 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -18,7 +18,7 @@ * */ -#include "cpu-qom.h" +#include "cpu.h" #include "qemu-common.h" diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 422a55b..da80469 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -186,7 +186,7 @@ struct CPULM32State { #include "cpu-qom.h" -CPULM32State *cpu_lm32_init(const char *cpu_model); +LM32CPU *cpu_lm32_init(const char *cpu_model); void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf); int cpu_lm32_exec(CPULM32State *s); void cpu_lm32_close(CPULM32State *s); @@ -199,8 +199,16 @@ int cpu_lm32_signal_handler(int host_signum, void *pinfo, void lm32_translate_init(void); void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value); +static inline CPULM32State *cpu_init(const char *cpu_model) +{ + LM32CPU *cpu = cpu_lm32_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + #define cpu_list cpu_lm32_list -#define cpu_init cpu_lm32_init #define cpu_exec cpu_lm32_exec #define cpu_gen_code cpu_lm32_gen_code #define cpu_signal_handler cpu_lm32_signal_handler diff --git a/target-lm32/helper.c b/target-lm32/helper.c index d0bc193..3b1cee7 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -192,7 +192,7 @@ static uint32_t cfg_by_def(const LM32Def *def) return cfg; } -CPULM32State *cpu_lm32_init(const char *cpu_model) +LM32CPU *cpu_lm32_init(const char *cpu_model) { LM32CPU *cpu; CPULM32State *env; @@ -219,7 +219,7 @@ CPULM32State *cpu_lm32_init(const char *cpu_model) lm32_translate_init(); } - return env; + return cpu; } /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory