===================================================================
@@ -7097,6 +7097,29 @@
}
[(set_attr "type" "cbranch")])
+;; The *branch_true patterns help combine when trying to invert conditions.
+(define_insn "*branch_true"
+ [(set (pc) (if_then_else (ne (zero_extend:SI (subreg:QI (reg:SI T_REG) 0))
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_SH1 && TARGET_LITTLE_ENDIAN"
+{
+ return output_branch (1, insn, operands);
+}
+ [(set_attr "type" "cbranch")])
+
+(define_insn "*branch_true"
+ [(set (pc) (if_then_else (ne (zero_extend:SI (subreg:QI (reg:SI T_REG) 3))
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN"
+{
+ return output_branch (1, insn, operands);
+}
+ [(set_attr "type" "cbranch")])
+
(define_insn "branch_false"
[(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
(label_ref (match_operand 0 "" ""))
@@ -7107,6 +7130,29 @@
}
[(set_attr "type" "cbranch")])
+;; The *branch_false patterns help combine when trying to invert conditions.
+(define_insn "*branch_false"
+ [(set (pc) (if_then_else (eq (zero_extend:SI (subreg:QI (reg:SI T_REG) 0))
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_SH1 && TARGET_LITTLE_ENDIAN"
+{
+ return output_branch (0, insn, operands);
+}
+ [(set_attr "type" "cbranch")])
+
+(define_insn "*branch_false"
+ [(set (pc) (if_then_else (eq (zero_extend:SI (subreg:QI (reg:SI T_REG) 3))
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN"
+{
+ return output_branch (0, insn, operands);
+}
+ [(set_attr "type" "cbranch")])
+
;; Patterns to prevent reorg from re-combining a condbranch with a branch
;; which destination is too far away.
;; The const_int_operand is distinct for each branch target; it avoids
@@ -9721,7 +9767,7 @@
""
[(const_int 0)])
-;; The *movtt patterns improve code at -O1.
+;; The *movtt patterns eliminate redundant T bit to T bit moves / tests.
(define_insn_and_split "*movtt"
[(set (reg:SI T_REG)
(eq:SI (zero_extend:SI (subreg:QI (reg:SI T_REG) 3))
Hello, The attached patch is the same as in the PR comment #37. Tested with make -k check RUNTESTFLAGS="--target_board=sh-sim \{-m2/-ml,-m2/-mb,-m2a/-mb,-m2a-single/-mb,-m4/-ml,-m4/-mb, -m4-single/-ml,-m4-single/-mb,-m4a-single/-ml,-m4a-single/-mb}" and no new failures. OK? Cheers, Oleg ChangeLog: PR target/51244 * config/sh/sh.md (*branch_true, *branch_false): New insns.