From patchwork Tue May 8 02:49:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Porter X-Patchwork-Id: 157556 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A7C7AB6FA7 for ; Tue, 8 May 2012 14:24:19 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E376A2807E; Tue, 8 May 2012 06:24:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wRLlQGkS5iLo; Tue, 8 May 2012 06:24:17 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 87FBC2807F; Tue, 8 May 2012 06:24:15 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D53CD2807E for ; Tue, 8 May 2012 04:49:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4gUAuWqOWT0m for ; Tue, 8 May 2012 04:49:28 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yx0-f172.google.com (mail-yx0-f172.google.com [209.85.213.172]) by theia.denx.de (Postfix) with ESMTPS id 025282807D for ; Tue, 8 May 2012 04:49:26 +0200 (CEST) Received: by yenq13 with SMTP id q13so1080471yen.3 for ; Mon, 07 May 2012 19:49:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer; bh=FX/ztNy/tvs6zQK0qgPtLqT/uX6vfuCq98gHVg1y05s=; b=S1xIWp+pMjv9yG8cmxPt4/Z05OPs/sY2/GN+0AVXRrRzn/MeIwHwtNeTd/qRout7N3 MgY9Yh/HOjKXvWyhIHep5EXOAyt1OXb5Irwmwf47KlrWI134oXQaHypGUmioumPh/61o c22haxq4XXO8Opr6O66p7klpnbfNVmL0hDzeCW8aPCOCfB3q7cxVXzeHJ9WUCcJH71rF JJa1JQOITGAAoHgTJJh1XdUMOQ+uaDtsDT/DNL2Ke3OiO6Z5nmoZvbgA+zg3/KIAg/n2 pAhlr/ebcxEf3YRqj00tQlSWJj/HZ+XKFRU9TSRah8EaI3j3el9oIYaaAz31fF41rdaA 5ArQ== Received: by 10.50.181.166 with SMTP id dx6mr9639771igc.61.1336445364089; Mon, 07 May 2012 19:49:24 -0700 (PDT) Received: from localhost.localdomain (cpe-24-166-64-7.neo.res.rr.com. [24.166.64.7]) by mx.google.com with ESMTPS id em4sm7552165igc.16.2012.05.07.19.49.22 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 07 May 2012 19:49:23 -0700 (PDT) From: Matt Porter To: U-Boot Mailing List Date: Mon, 7 May 2012 22:49:21 -0400 Message-Id: <1336445361-7762-1-git-send-email-mporter@ti.com> X-Mailer: git-send-email 1.7.5.4 X-Mailman-Approved-At: Tue, 08 May 2012 06:24:13 +0200 Cc: Tom Rini , Sandeep Paulraj Subject: [U-Boot] [PATCH] arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter --- arch/arm/cpu/armv7/omap3/clock.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 567817e..09c51f6 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -572,6 +572,22 @@ void prcm_init(void) } if (get_cpu_family() == CPU_OMAP36XX) { + /* + * In warm reset conditions on OMAP36xx/AM/DM37xx + * the rom code incorrectly sets the DPLL4 clock + * input divider to /6.5. Section 3.5.3.3.3.2.1 of + * the AM/DM37x TRM explains that the /6.5 divider + * is used only when the input clock is 13MHz. + * + * If the part is in this cpu family *and* the input + * clock *is not* 13 MHz, then reset the DPLL4 clock + * input divider to /1 as it should never set to /6.5 + * in this case. + */ + if (sys_clkin_sel != 1) /* 13 MHz */ + /* Bit 8: DPLL4_CLKINP_DIV */ + sr32(&prm_base->clksrc_ctrl, 8, 1, 0); + /* Unlock MPU DPLL (slows things down, and needed later) */ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,