[U-Boot,V2,RESEND,15/24] SPEAr: Enable dcache for fast file transfer

Submitted by Amit Virdi on May 7, 2012, 7:36 a.m.

Details

Message ID 5272d4a8672937f431c3c340a7a20801dfdeb231.1336376035.git.amit.virdi@st.com
State Accepted
Delegated to: Stefan Roese
Headers show

Commit Message

Amit Virdi May 7, 2012, 7:36 a.m.
From: Shiraz Hashim <shiraz.hashim@st.com>

Enable data cache with 1:1 mapping of DDR to enable fast file
transfer over tty which was doing lot of copy.

This feature is enabled only for flashing operation i.e. when
CONFIG_SPEAR_USBTTY is enabled.

This has been tested on SPEAr320, SPEAr600 and SPEAr900 evaluation
boards.

Following figures show an estimate on the performance improvements. The
test setup was a Linux host (not Windows) and involved measurement of
only binary transfer time, through kermit. The flash erase and flash
copy time would be unaffected by these patches.

Another thing is this that the timings remained more or less same across
ARM9 and Cortex based devices, hence reporting only one of the cases.

Before Enhancements

Patch hide | download patch | download mbox

===================

$ time ukermit.small -p /dev/ttyACM0 -f spear320_uImage.img
Downloading file: 100.00% completed(2014080/2014080 bytes)
real    0m41.228s
user    0m0.002s
sys     0m0.064s

After Enhancements
==================

$ time ukermit.large -p /dev/ttyACM0 -f spear320_uImage.img
Downloading file: 100.00% completed(2014080/2014080 bytes)
real    0m5.441s
user    0m0.001s
sys     0m0.001s

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
---
 board/spear/common/spr_misc.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index 043c72a..99a6595 100644
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -76,6 +76,10 @@  int misc_init_r(void)
 	setenv("stdin", "usbtty");
 	setenv("stdout", "usbtty");
 	setenv("stderr", "usbtty");
+
+#ifndef CONFIG_SYS_NO_DCACHE
+	dcache_enable();
+#endif
 #endif
 	return 0;
 }