From patchwork Tue May 1 12:20:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohammed Afzal X-Patchwork-Id: 156099 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CEF28B6FA8 for ; Tue, 1 May 2012 23:04:36 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SPCj3-0001zj-2z; Tue, 01 May 2012 13:02:42 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SPCKl-0007aE-IR; Tue, 01 May 2012 12:37:38 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q41CbOtE025704; Tue, 1 May 2012 07:37:24 -0500 Received: from DFLE70.ent.ti.com (dfle70.ent.ti.com [128.247.5.40]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q41CbO3S026082; Tue, 1 May 2012 07:37:24 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle70.ent.ti.com (128.247.5.40) with Microsoft SMTP Server id 14.1.323.3; Tue, 1 May 2012 07:37:24 -0500 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with SMTP id q41CbIkL011504; Tue, 1 May 2012 07:37:19 -0500 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id 07DCF158002; Tue, 1 May 2012 18:07:18 +0530 (IST) Received: from linux-psp-server.india.ext.ti.com (linux-psp-server [192.168.247.76]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id q41CbHI18603; Tue, 1 May 2012 18:07:17 +0530 (IST) From: Afzal Mohammed To: , , , , , , , , , , , , , , , , Subject: [PATCH v4 08/39] ARM: OMAP2+: gpmc-onenand: Adapt to use gpmc driver Date: Tue, 1 May 2012 17:50:34 +0530 Message-ID: <22c26038c318cc6548c108a6958e712cc387863e.1335874494.git.afzal@ti.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.40 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Afzal Mohammed X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Currently gpmc is configured in platform for onenand. As configuring gpmc has been moved to gpmc driver, populate details needed for the driver to configure gpmc. gpmc driver would configure based on this information. Signed-off-by: Afzal Mohammed --- arch/arm/mach-omap2/gpmc-onenand.c | 111 +++++++++++++++-------------- arch/arm/plat-omap/include/plat/onenand.h | 7 +- 2 files changed, 61 insertions(+), 57 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index a0fa9bb..d7775d5 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -25,9 +25,17 @@ static struct omap_onenand_platform_data *gpmc_onenand_data; -static struct platform_device gpmc_onenand_device = { +#define ONENAND_IO_SIZE SZ_128K + +static struct gpmc_cs_data gpmc_onenand_cs_info = { + .mem_size = ONENAND_IO_SIZE, +}; + +static struct gpmc_device_pdata gpmc_onenand_info = { .name = "omap2-onenand", .id = -1, + .cs_data = &gpmc_onenand_cs_info, + .num_cs = 1, }; static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) @@ -79,13 +87,17 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez); /* Configure GPMC for asynchronous read */ - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, - GPMC_CONFIG1_DEVICESIZE_16 | - GPMC_CONFIG1_MUXADDDATA); - - err = gpmc_cs_set_timings(cs, &t); - if (err) + gpmc_onenand_cs_info.have_config = true; + gpmc_onenand_cs_info.config = GPMC_DEVICESIZE_16 | + GPMC_MUXADDDATA | + GPMC_DEVICETYPE_NOR; + gpmc_onenand_cs_info.timing = &t; + err = gpmc_cs_reconfigure(gpmc_onenand_info.name, + gpmc_onenand_info.id, &gpmc_onenand_cs_info); + if (err) { + pr_err("%s: gpmc_cs_reconfigure failed\n", __func__); return err; + } /* Ensure sync read and sync write are disabled */ reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); @@ -180,7 +192,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; int err, ticks_cez; int cs = cfg->cs, freq = *freq_ptr; - u32 reg; bool clk_dep = false; if (cfg->flags & ONENAND_SYNC_READ) { @@ -276,27 +287,10 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, sync_read, sync_write, hf, vhf); if (div == 1) { - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); - reg |= (1 << 7); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg); - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3); - reg |= (1 << 7); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg); - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4); - reg |= (1 << 7); - reg |= (1 << 23); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg); - } else { - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); - reg &= ~(1 << 7); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg); - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3); - reg &= ~(1 << 7); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg); - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4); - reg &= ~(1 << 7); - reg &= ~(1 << 23); - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg); + t.control.cs_extra_delay = true; + t.control.adv_extra_delay = true; + t.control.oe_extra_delay = true; + t.control.we_extra_delay = true; } /* Set synchronous read timings */ @@ -348,24 +342,31 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, } /* Configure GPMC for synchronous read */ - gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, - GPMC_CONFIG1_WRAPBURST_SUPP | - GPMC_CONFIG1_READMULTIPLE_SUPP | - (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) | - (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) | - (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) | - GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) | - GPMC_CONFIG1_PAGE_LEN(2) | - (cpu_is_omap34xx() ? 0 : - (GPMC_CONFIG1_WAIT_READ_MON | - GPMC_CONFIG1_WAIT_PIN_SEL(0))) | - GPMC_CONFIG1_DEVICESIZE_16 | - GPMC_CONFIG1_DEVICETYPE_NOR | - GPMC_CONFIG1_MUXADDDATA); - - err = gpmc_cs_set_timings(cs, &t); - if (err) + gpmc_onenand_cs_info.have_config = true; + gpmc_onenand_cs_info.config = GPMC_DEVICESIZE_16 | GPMC_MUXADDDATA | + GPMC_DEVICETYPE_NOR | GPMC_WRAPBURST | + GPMC_READMULTIPLE | GPMC_PAGE_LEN_16; + if (!cpu_is_omap34xx()) + gpmc_onenand_cs_info.config |= GPMC_WAIT_READ_MON | + GPMC_WAITPIN_0; + if (sync_read) + gpmc_onenand_cs_info.config |= GPMC_READTYPE_SYNC; + if (sync_write) + gpmc_onenand_cs_info.config |= GPMC_WRITETYPE_SYNC | + GPMC_WRITEMULTIPLE; + if (fclk_offset == 0) + gpmc_onenand_cs_info.config |= GPMC_CLOCKACTIVATIONTIME_0; + else if (fclk_offset == 1) + gpmc_onenand_cs_info.config |= GPMC_CLOCKACTIVATIONTIME_1; + else if (fclk_offset == 2) + gpmc_onenand_cs_info.config |= GPMC_CLOCKACTIVATIONTIME_2; + gpmc_onenand_cs_info.timing = &t; + err = gpmc_cs_reconfigure(gpmc_onenand_info.name, + gpmc_onenand_info.id, &gpmc_onenand_cs_info); + if (err) { + pr_err("%s: gpmc_cs_reconfigure failed\n", __func__); return err; + } set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); @@ -376,23 +377,21 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) { - struct device *dev = &gpmc_onenand_device.dev; - /* Set sync timings in GPMC */ if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, freq_ptr) < 0) { - dev_err(dev, "Unable to set synchronous mode\n"); + pr_err("%s: Unable to set synchronous mode\n", __func__); return -EINVAL; } return 0; } -void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) +struct gpmc_device_pdata * +__init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) { gpmc_onenand_data = _onenand_data; gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; - gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; if (cpu_is_omap24xx() && (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) { @@ -401,8 +400,10 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) gpmc_onenand_data->flags |= ONENAND_SYNC_READ; } - if (platform_device_register(&gpmc_onenand_device) < 0) { - printk(KERN_ERR "Unable to register OneNAND device\n"); - return; - } + gpmc_onenand_info.pdata = gpmc_onenand_data; + gpmc_onenand_info.pdata_size = sizeof(*gpmc_onenand_data); + + gpmc_onenand_cs_info.cs = gpmc_onenand_data->cs; + + return &gpmc_onenand_info; } diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h index 2858667..47cd710 100644 --- a/arch/arm/plat-omap/include/plat/onenand.h +++ b/arch/arm/plat-omap/include/plat/onenand.h @@ -40,14 +40,17 @@ struct omap_onenand_platform_data { #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) -extern void gpmc_onenand_init(struct omap_onenand_platform_data *d); +extern struct gpmc_device_pdata * +gpmc_onenand_init(struct omap_onenand_platform_data *d); #else #define board_onenand_data NULL -static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d) +static inline struct gpmc_device_pdata * +gpmc_onenand_init(struct omap_onenand_platform_data *d) { + return NULL; } #endif