From patchwork Tue May 1 12:20:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohammed Afzal X-Patchwork-Id: 156095 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D44FAB6FA8 for ; Tue, 1 May 2012 23:01:33 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SPCfj-0007jt-9O; Tue, 01 May 2012 12:59:16 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SPCKI-0007DK-BP; Tue, 01 May 2012 12:37:09 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q41CatND019906; Tue, 1 May 2012 07:36:55 -0500 Received: from DFLE70.ent.ti.com (dfle70.ent.ti.com [128.247.5.40]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q41Catom025612; Tue, 1 May 2012 07:36:55 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle70.ent.ti.com (128.247.5.40) with Microsoft SMTP Server id 14.1.323.3; Tue, 1 May 2012 07:36:55 -0500 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with SMTP id q41CanXx011272; Tue, 1 May 2012 07:36:50 -0500 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id EAD7C158002; Tue, 1 May 2012 18:06:48 +0530 (IST) Received: from linux-psp-server.india.ext.ti.com (linux-psp-server [192.168.247.76]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id q41CamI18585; Tue, 1 May 2012 18:06:48 +0530 (IST) From: Afzal Mohammed To: , , , , , , , , , , , , , , , , Subject: [PATCH v4 04/39] ARM: OMAP2+: gpmc: Acquire NAND CS value Date: Tue, 1 May 2012 17:50:05 +0530 Message-ID: <10220de398d22fad5de783d8f58fc55ebac85338.1335874494.git.afzal@ti.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Afzal Mohammed X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Some boards depend on bootloader to update chip select value for NAND. It is felt that Kernel should not depend on bootloader to get CS, as for a particular board CS is hardwired and is fixed, hence this can directly be updated in Kernel. But as CS value for boards that depend on this behaviour is not available, educate gpmc driver to acquire chip select value for NAND. this ideally should be removed once CS for those boards are available. Signed-off-by: Afzal Mohammed --- arch/arm/mach-omap2/gpmc.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 657ce95..ecd3384 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -892,6 +892,30 @@ static int __init gpmc_init(void) } postcore_initcall(gpmc_init); +static __devinit int gpmc_acquire_nand_cs(struct gpmc *gpmc, + struct gpmc_device_pdata *gdp) +{ + int cs = 0; + struct omap_nand_platform_data *nand = gdp->pdata; + + if ((nand->cs >= 0) && (nand->cs < GPMC_CS_NUM)) + return 0; + + while (cs < GPMC_CS_NUM) { + u32 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + + if ((l & GPMC_CONFIG1_DEVICETYPE(~0)) == + GPMC_CONFIG1_DEVICETYPE_NAND) { + dev_info(gpmc->dev, "found NAND on CS: %d\n", cs); + nand->cs = cs; + gdp->cs_data->cs = cs; + return 0; + } + cs++; + } + return -ENODEV; +} + static __devinit void gpmc_update_nand_reg(struct gpmc *gpmc, struct omap_nand_platform_data *nand) { @@ -1450,8 +1474,14 @@ static __devinit int gpmc_probe(struct platform_device *pdev) for (i = 0, gdq = gp->device_pdata, gd = gpmc->device; (i < gp->num_device) && (*gdq); i++, gdq++) { - if ((*gdq)->is_nand) + if ((*gdq)->is_nand) { + ret = gpmc_acquire_nand_cs(gpmc, *gdq); + if (IS_ERR_VALUE(ret)) { + dev_err(gpmc->dev, "CS error: %d\n", ret); + continue; + } gpmc_update_nand_reg(gpmc, (*gdq)->pdata); + } ret = gpmc_setup_device(gpmc, gd, *gdq); if (IS_ERR_VALUE(ret)) dev_err(gpmc->dev, "gpmc setup on %s failed\n",