===================================================================
@@ -6814,29 +6814,29 @@
(set_attr "mode" "SI")])
(define_insn "*umul<mode><dwi>3_1"
- [(set (match_operand:<DWI> 0 "register_operand" "=A,r")
+ [(set (match_operand:<DWI> 0 "register_operand" "=r,A")
(mult:<DWI>
(zero_extend:<DWI>
- (match_operand:DWIH 1 "nonimmediate_operand" "%0,d"))
+ (match_operand:DWIH 1 "nonimmediate_operand" "%d,0"))
(zero_extend:<DWI>
(match_operand:DWIH 2 "nonimmediate_operand" "rm,rm"))))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
- mul{<imodesuffix>}\t%2
- #"
- [(set_attr "isa" "*,bmi2")
- (set_attr "type" "imul,imulx")
- (set_attr "length_immediate" "0,*")
+ #
+ mul{<imodesuffix>}\t%2"
+ [(set_attr "isa" "bmi2,*")
+ (set_attr "type" "imulx,imul")
+ (set_attr "length_immediate" "*,0")
(set (attr "athlon_decode")
- (cond [(eq_attr "alternative" "0")
+ (cond [(eq_attr "alternative" "1")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double"))]
(const_string "*")))
- (set_attr "amdfam10_decode" "double,*")
- (set_attr "bdver1_decode" "direct,*")
- (set_attr "prefix" "orig,vex")
+ (set_attr "amdfam10_decode" "*,double")
+ (set_attr "bdver1_decode" "*,direct")
+ (set_attr "prefix" "vex,orig")
(set_attr "mode" "<MODE>")])
;; Convert mul to the mulx pattern to avoid flags dependency.
Hello! On BMI2 targets, we prefer mulx, so switch places of constraints 0 and 1. 2012-04-30 Uros Bizjak <ubizjak@gmail.com> PR target/53141 * config/i386/i386.md (*umul<mode><dwi>3_1): Switch places of constraints 0 and 1. Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline SVN. Uros.