@@ -1,5 +1,12 @@
2012-04-26 David S. Miller <davem@davemloft.net>
+ * config/sparc/niagara4.md: New file.
+ * config/sparc/sparc.md: Include it.
+ * config/sparc/sparc.c (niagara4_costs): New processor costs.
+ (sparc_option_override): Use it.
+ (sparc_use_sched_lookahead): Return 2 for niagara4.
+ (sparc_issue_rate): Likewise.
+
* config/sparc/sparc.md (attr type): Delete 'fgm_cmp'.
(fpack16_vis, fpackfix_vis, fpack32_vis): Set type to fgm_pack.
(fmul8x16_vis, fmul8x16au_vis, fmul8x16al_vis, fmul8sux16_vis,
new file mode 100644
@@ -0,0 +1,83 @@
+;; Scheduling description for Niagara-4
+;; Copyright (C) 2012 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "niagara4_0")
+
+(define_cpu_unit "n4_slot0,n4_slot1" "niagara4_0")
+(define_reservation "n4_single_issue" "n4_slot0 + n4_slot1")
+
+(define_insn_reservation "n4_single" 1
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "multi,savew,flushw,iflush,trap,gsr"))
+ "n4_single_issue")
+
+(define_insn_reservation "n4_integer" 1
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "ialu,ialuX,shift,cmove,compare"))
+ "(n4_slot0 | n4_slot1)")
+
+(define_insn_reservation "n4_imul" 12
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "imul"))
+ "(n4_slot0 | n4_slot1), nothing*11")
+
+(define_insn_reservation "n4_idiv" 35
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "idiv"))
+ "(n4_slot0 | n4_slot1), nothing*34")
+
+(define_insn_reservation "n4_load" 5
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "load,fpload,sload"))
+ "n4_slot0, nothing*4")
+
+(define_insn_reservation "n4_store" 1
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "store,fpstore"))
+ "n4_slot0")
+
+(define_insn_reservation "n4_cti" 2
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "branch,call,sibcall,call_no_delay_slot,uncond_branch,return"))
+ "n4_slot1, nothing")
+
+(define_insn_reservation "n4_fp" 11
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul"))
+ "n4_slot1, nothing*10")
+
+(define_insn_reservation "n4_array" 12
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "array,edge,edgen"))
+ "n4_slot1, nothing*11")
+
+(define_insn_reservation "n4_vis" 11
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist"))
+ "n4_slot1, nothing*10")
+
+(define_insn_reservation "n4_fpdivs" 24
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "fpdivs,fpsqrts"))
+ "n4_slot1, nothing*23")
+
+(define_insn_reservation "n4_fpdivd" 37
+ (and (eq_attr "cpu" "niagara4")
+ (eq_attr "type" "fpdivd,fpsqrtd"))
+ "n4_slot1, nothing*36")
@@ -374,6 +374,30 @@ struct processor_costs niagara3_costs = {
0, /* shift penalty */
};
+static const
+struct processor_costs niagara4_costs = {
+ COSTS_N_INSNS (5), /* int load */
+ COSTS_N_INSNS (5), /* int signed load */
+ COSTS_N_INSNS (5), /* int zeroed load */
+ COSTS_N_INSNS (5), /* float load */
+ COSTS_N_INSNS (11), /* fmov, fneg, fabs */
+ COSTS_N_INSNS (11), /* fadd, fsub */
+ COSTS_N_INSNS (11), /* fcmp */
+ COSTS_N_INSNS (11), /* fmov, fmovr */
+ COSTS_N_INSNS (11), /* fmul */
+ COSTS_N_INSNS (24), /* fdivs */
+ COSTS_N_INSNS (37), /* fdivd */
+ COSTS_N_INSNS (24), /* fsqrts */
+ COSTS_N_INSNS (37), /* fsqrtd */
+ COSTS_N_INSNS (12), /* imul */
+ COSTS_N_INSNS (12), /* imulX */
+ 0, /* imul bit factor */
+ COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
+ COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
+ COSTS_N_INSNS (1), /* movcc/movr */
+ 0, /* shift penalty */
+};
+
static const struct processor_costs *sparc_costs = &cypress_costs;
#ifdef HAVE_AS_RELAX_OPTION
@@ -1157,9 +1181,11 @@ sparc_option_override (void)
sparc_costs = &niagara2_costs;
break;
case PROCESSOR_NIAGARA3:
- case PROCESSOR_NIAGARA4:
sparc_costs = &niagara3_costs;
break;
+ case PROCESSOR_NIAGARA4:
+ sparc_costs = &niagara4_costs;
+ break;
case PROCESSOR_NATIVE:
gcc_unreachable ();
};
@@ -8890,9 +8916,10 @@ sparc_use_sched_lookahead (void)
{
if (sparc_cpu == PROCESSOR_NIAGARA
|| sparc_cpu == PROCESSOR_NIAGARA2
- || sparc_cpu == PROCESSOR_NIAGARA3
- || sparc_cpu == PROCESSOR_NIAGARA4)
+ || sparc_cpu == PROCESSOR_NIAGARA3)
return 0;
+ if (sparc_cpu == PROCESSOR_NIAGARA4)
+ return 2;
if (sparc_cpu == PROCESSOR_ULTRASPARC
|| sparc_cpu == PROCESSOR_ULTRASPARC3)
return 4;
@@ -8911,9 +8938,9 @@ sparc_issue_rate (void)
case PROCESSOR_NIAGARA:
case PROCESSOR_NIAGARA2:
case PROCESSOR_NIAGARA3:
- case PROCESSOR_NIAGARA4:
default:
return 1;
+ case PROCESSOR_NIAGARA4:
case PROCESSOR_V9:
/* Assume V9 processors are capable of at least dual-issue. */
return 2;
@@ -477,6 +477,7 @@
(include "ultra3.md")
(include "niagara.md")
(include "niagara2.md")
+(include "niagara4.md")
;; Operand and operator predicates and constraints