Patchwork [U-Boot] powerpc/mpc85xx:Add debugger support for P1010 and P1014

login
register
mail settings
Submitter Prabhakar Kushwaha
Date April 25, 2012, 8:26 a.m.
Message ID <1335342380-28607-1-git-send-email-prabhakar@freescale.com>
Download mbox | patch
Permalink /patch/154832/
State Superseded
Delegated to: Andy Fleming
Headers show

Comments

Prabhakar Kushwaha - April 25, 2012, 8:26 a.m.
P1010 and P1014 SoC has e500v2 processor.
And Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).

So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.
Please refer doc/README.mpc85xx for more information

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 arch/powerpc/include/asm/config_mpc85xx.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

Patch

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 8654625..5a70be7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -107,6 +107,7 @@ 
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_FSL_SATA_V2
@@ -160,6 +161,7 @@ 
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_FSL_SATA_V2