From patchwork Thu Apr 19 14:19:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 153777 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 902EDB6FD3 for ; Fri, 20 Apr 2012 00:19:44 +1000 (EST) Received: from localhost ([::1]:46880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SKsD0-0007U1-BZ for incoming@patchwork.ozlabs.org; Thu, 19 Apr 2012 10:19:42 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SKsCl-0007Lf-My for qemu-devel@nongnu.org; Thu, 19 Apr 2012 10:19:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SKsCf-0000cT-BU for qemu-devel@nongnu.org; Thu, 19 Apr 2012 10:19:27 -0400 Received: from cantor2.suse.de ([195.135.220.15]:39854 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SKsCf-0000cD-2b; Thu, 19 Apr 2012 10:19:21 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 97130938E3; Thu, 19 Apr 2012 16:19:19 +0200 (CEST) From: Alexander Graf To: qemu-devel qemu-devel Date: Thu, 19 Apr 2012 16:19:16 +0200 Message-Id: <1334845156-23988-1-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: scottwood@freescale.com, Varun.Sethi@freescale.com, meadori@codesourcery.com, qemu-ppc@nongnu.org, afaerber@suse.de Subject: [Qemu-devel] [PATCH] PPC: Fix up e500 cache size setting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When initializing the e500 code, we need to expose its cache line size for user and system mode, while the mmu details are only interesting for system emulation. Split the 2 switch statements apart, allowing us to #ifdef out the mmu parts for user mode emulation while keeping all cache information consistent. Signed-off-by: Alexander Graf --- target-ppc/translate_init.c | 26 ++++++++++++++------------ 1 files changed, 14 insertions(+), 12 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index ba4b84d..6f61175 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -4461,33 +4461,36 @@ static void init_proc_e500 (CPUPPCState *env, int version) &spr_read_spefscr, &spr_write_spefscr, &spr_read_spefscr, &spr_write_spefscr, 0x00000000); +#if !defined(CONFIG_USER_ONLY) /* Memory management */ -#if defined(CONFIG_USER_ONLY) - env->dcache_line_size = 32; - env->icache_line_size = 32; -#else /* !defined(CONFIG_USER_ONLY) */ env->nb_pids = 3; env->nb_ways = 2; env->id_tlbs = 0; switch (version) { case fsl_e500v1: - /* e500v1 */ tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); - env->dcache_line_size = 32; - env->icache_line_size = 32; break; case fsl_e500v2: - /* e500v2 */ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); - env->dcache_line_size = 32; - env->icache_line_size = 32; break; case fsl_e500mc: - /* e500mc */ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); + break; + default: + cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); + } +#endif + /* Cache sizes */ + switch (version) { + case fsl_e500v1: + case fsl_e500v2: + env->dcache_line_size = 32; + env->icache_line_size = 32; + break; + case fsl_e500mc: env->dcache_line_size = 64; env->icache_line_size = 64; l1cfg0 |= 0x1000000; /* 64 byte cache block size */ @@ -4495,7 +4498,6 @@ static void init_proc_e500 (CPUPPCState *env, int version) default: cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } -#endif gen_spr_BookE206(env, 0x000000DF, tlbncfg); /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0",