Patchwork [U-Boot,PATCHv2] e1000e : Correct Rx Threshold granularity

login
register
mail settings
Submitter Ruchika Gupta
Date April 19, 2012, 12:27 p.m.
Message ID <1334838431-14516-1-git-send-email-ruchika.gupta@freescale.com>
Download mbox | patch
Permalink /patch/153657/
State Accepted
Delegated to: Joe Hershberger
Headers show

Comments

Ruchika Gupta - April 19, 2012, 12:27 p.m.
In e1000e driver, Rx descriptor queue is used such that hardware can add only 
one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set 
to single descriptor. This would ensure that every time controller fills a Rx 
descriptor, it is flushed to host memory. Earlier this granularity was in 
cache line units i.e 2 descriptors. This leads to controller always waiting 
for 2 descriptors before flushing them out. But since not more than one Rx BD 
is actually available , the accumulation condition never gets hit.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
---
Tested on P1010 and P4080 with 82572 and 82574 cards.

Changes in v2
	- Fixed subject line and commit message

 drivers/net/e1000.c |   10 ++++++++++
 drivers/net/e1000.h |    1 +
 2 files changed, 11 insertions(+), 0 deletions(-)

Patch

diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 98145bc..1f3c2b0 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1703,6 +1703,16 @@  e1000_init_hw(struct eth_device *nic)
 		E1000_WRITE_REG(hw, TXDCTL, ctrl);
 	}
 
+	/* Set the receive descriptor write back policy */
+
+	if (hw->mac_type >= e1000_82571) {
+		ctrl = E1000_READ_REG(hw, RXDCTL);
+		ctrl =
+		    (ctrl & ~E1000_RXDCTL_WTHRESH) |
+		    E1000_RXDCTL_FULL_RX_DESC_WB;
+		E1000_WRITE_REG(hw, RXDCTL, ctrl);
+	}
+
 	switch (hw->mac_type) {
 	default:
 		break;
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 720d8c6..cdb0e36 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -1518,6 +1518,7 @@  struct e1000_hw {
 #define E1000_RXDCTL_HTHRESH 0x00003F00	/* RXDCTL Host Threshold */
 #define E1000_RXDCTL_WTHRESH 0x003F0000	/* RXDCTL Writeback Threshold */
 #define E1000_RXDCTL_GRAN    0x01000000	/* RXDCTL Granularity */
+#define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000	/* GRAN=1, WTHRESH=1 */
 
 /* Transmit Descriptor Control */
 #define E1000_TXDCTL_PTHRESH 0x0000003F	/* TXDCTL Prefetch Threshold */