From patchwork Tue Apr 17 12:50:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Starikovskiy X-Patchwork-Id: 153164 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 05D2EB6FE2 for ; Tue, 17 Apr 2012 22:50:37 +1000 (EST) Received: from localhost ([::1]:52166 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SK7rd-0002B8-PH for incoming@patchwork.ozlabs.org; Tue, 17 Apr 2012 08:50:33 -0400 Received: from eggs.gnu.org ([208.118.235.92]:54353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SK7rS-0002AM-Ny for qemu-devel@nongnu.org; Tue, 17 Apr 2012 08:50:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SK7rI-0005jK-7D for qemu-devel@nongnu.org; Tue, 17 Apr 2012 08:50:22 -0400 Received: from mail-we0-f173.google.com ([74.125.82.173]:52073) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SK7rH-0005gc-R8 for qemu-devel@nongnu.org; Tue, 17 Apr 2012 08:50:12 -0400 Received: by werp12 with SMTP id p12so4644403wer.4 for ; Tue, 17 Apr 2012 05:50:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=Egzizwe+H8WRUo0tLo1o446TxqfS9irzFX60s93c4ZI=; b=z49KE7unV4GLx/ftcGuR7dPqUoD7pkW2XZSCRAxqeE/kSsuiRo5wwxiKTlVW7lhVRO CBay4D8UvVQI1l7SHmqsKMW2WXxF5+1NOOQhLPWS17sdJbAhKGbBF411JX/7PrvqC2Jg oWiPlOUccFvTD1BFpDePc/UkqIh9nhuufZ7VamxLUH2QHBjZdlphrGttrMp+yqP2NAKk 3lw6oJIS2ptbBUr7A/rcEPyF1vhG90k6l2LbqnVuhtjFRna0uL9Yu7wr+Dqd8b27Sq8R gTFXp7o2YOhgjCkLljOFJp1FloByaQJ1Psu3hPmoE2DHho1LTInY9M/Yj276x4zOehvC vVZg== MIME-Version: 1.0 Received: by 10.216.136.100 with SMTP id v78mr9302963wei.88.1334667009762; Tue, 17 Apr 2012 05:50:09 -0700 (PDT) Received: by 10.180.8.136 with HTTP; Tue, 17 Apr 2012 05:50:09 -0700 (PDT) In-Reply-To: References: <4F8D5664.7000304@gmail.com> <4F8D5BFE.40204@gmail.com> Date: Tue, 17 Apr 2012 16:50:09 +0400 Message-ID: From: Alexey Starikovskiy To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 74.125.82.173 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v3] Undefine SWP instruction unless SCTLR.SW bit is set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org ARM v7MP deprecates use of SWP instruction and only defines it if OS explicitly requests it via setting SCTLR.SW bit. Such a request is expected to occur only once during OS init, thus only static checking for this bit and flush of all translations is done on SCTLR change. Signed-off-by: Alexey Starikovskiy --- target-arm/helper.c | 7 +++++-- target-arm/translate.c | 10 ++++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 28f127b..2451eba 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1486,11 +1486,14 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) op2 = 0; switch (op2) { case 0: - if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0) + if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0) { env->cp15.c1_sys = val; /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(env, 1); + tlb_flush(env, 1); + /* This may enable/disable SWP instruction, so do TB flush too */ + tb_flush(env); + } break; case 1: /* Auxiliary control register. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { diff --git a/target-arm/translate.c b/target-arm/translate.c index 7a3c7d6..4f17fd0 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7415,6 +7415,16 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) } tcg_temp_free(addr); } else { +/* User mode allows superset of all ARM instructions, thus disable check */ +#ifndef CONFIG_USER_ONLY + if (arm_feature(env, ARM_FEATURE_V7MP) && + !(env->cp15.c1_sys & (1 << 10))) { + /* Check if SCTLR.SW is set. Any change to SCTLR + * invalidates all translations, so we are safe. + */ + goto illegal_op; + } +#endif /* SWP instruction */ rm = (insn) & 0xf;