@@ -21,6 +21,7 @@
#include "apic_internal.h"
#include "trace.h"
#include "kvm.h"
+#include "msi.h"
static int apic_irq_delivered;
bool apic_report_tpr_access;
@@ -284,6 +285,7 @@ static int apic_init_common(SysBusDevice *dev)
APICCommonClass *info;
static DeviceState *vapic;
static int apic_no;
+ static int apic_mapped;
if (apic_no >= MAX_APICS) {
return -1;
@@ -295,6 +297,20 @@ static int apic_init_common(SysBusDevice *dev)
sysbus_init_mmio(dev, &s->io_memory);
+ /* XXX: mapping more APICs at the same memory location */
+ if (apic_mapped == 0) {
+ /* NOTE: the APIC is directly connected to the CPU - it is not
+ on the global memory bus. */
+ /* XXX: what if the base changes? */
+ sysbus_mmio_map(sysbus_from_qdev(&s->busdev.qdev), 0, MSI_ADDR_BASE);
+ apic_mapped = 1;
+ }
+
+ /* KVM does not support MSI yet. */
+ if (!kvm_irqchip_in_kernel()) {
+ msi_supported = true;
+ }
+
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK) {
vapic = sysbus_create_simple("kvmvapic", -1, NULL);
}
@@ -40,4 +40,6 @@ static inline bool msi_present(const PCIDevice *dev)
return dev->cap_present & QEMU_PCI_CAP_MSI;
}
+#define MSI_ADDR_BASE 0xfee00000
+
#endif /* QEMU_MSI_H */
@@ -878,37 +878,6 @@ DeviceState *cpu_get_current_apic(void)
}
}
-static DeviceState *apic_init(void *env, uint8_t apic_id)
-{
- DeviceState *dev;
- static int apic_mapped;
-
- if (kvm_irqchip_in_kernel()) {
- dev = qdev_create(NULL, "kvm-apic");
- } else {
- dev = qdev_create(NULL, "apic");
- }
- qdev_prop_set_uint8(dev, "id", apic_id);
- qdev_prop_set_ptr(dev, "cpu_env", env);
- qdev_init_nofail(dev);
-
- /* XXX: mapping more APICs at the same memory location */
- if (apic_mapped == 0) {
- /* NOTE: the APIC is directly connected to the CPU - it is not
- on the global memory bus. */
- /* XXX: what if the base changes? */
- sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
- apic_mapped = 1;
- }
-
- /* KVM does not support MSI yet. */
- if (!kvm_irqchip_in_kernel()) {
- msi_supported = true;
- }
-
- return dev;
-}
-
void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
{
CPUX86State *s = opaque;
@@ -934,7 +903,15 @@ static CPUX86State *pc_new_cpu(const char *cpu_model)
exit(1);
}
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
- env->apic_state = apic_init(env, env->cpuid_apic_id);
+ if (kvm_irqchip_in_kernel()) {
+ env->apic_state = qdev_create(NULL, "kvm-apic");
+ } else {
+ env->apic_state = qdev_create(NULL, "apic");
+ }
+ qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
+ qdev_prop_set_ptr(env->apic_state, "cpu_env", env);
+ qdev_init_nofail(env->apic_state);
+
/* We hard-wire the BSP to the first CPU. */
if (env->cpu_index == 0) {
apic_designate_bsp(env->apic_state);