From patchwork Mon Apr 16 01:39:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hao, Xudong" X-Patchwork-Id: 152738 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id F0236B6FBB for ; Mon, 16 Apr 2012 11:43:10 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752605Ab2DPBnG (ORCPT ); Sun, 15 Apr 2012 21:43:06 -0400 Received: from mga14.intel.com ([143.182.124.37]:11875 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752600Ab2DPBnF convert rfc822-to-8bit (ORCPT ); Sun, 15 Apr 2012 21:43:05 -0400 Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga102.ch.intel.com with ESMTP; 15 Apr 2012 18:43:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="89381428" Received: from azsmsx601.amr.corp.intel.com ([10.2.121.193]) by AZSMGA002.ch.intel.com with ESMTP; 15 Apr 2012 18:43:04 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by azsmsx601.amr.corp.intel.com (10.2.121.193) with Microsoft SMTP Server (TLS) id 8.2.255.0; Sun, 15 Apr 2012 18:43:04 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.125]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.195]) with mapi id 14.01.0355.002; Mon, 16 Apr 2012 09:39:42 +0800 From: "Hao, Xudong" To: Bjorn Helgaas CC: "linux-pci@vger.kernel.org" , Don Dutile , Matthew Wilcox Subject: [PATCH v6] Quirk for IVB graphics FLR errata Thread-Topic: [PATCH v6] Quirk for IVB graphics FLR errata Thread-Index: Ac0bcXgCIqB/jRP1RGavlc5JaQ81UA== Date: Mon, 16 Apr 2012 01:39:41 +0000 Message-ID: <403610A45A2B5242BD291EDAE8B37D300FD11823@SHSMSX102.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org For IvyBridge Mobile platform, a system hang may occur if a FLR(Function Level Reset) is asserted to internal graphics. This quirk patch is workaround for the IVB FLR errata issue. We are disabling the FLR reset handshake between the PCH and CPU display, then manually powering down the panel power sequencing and resetting the PCH display. Changes from v5: - clean up patch with Matthew's comments. Signed-off-by: Xudong Hao Signed-off-by: Kay, Allen M Signed-off-by: Matthew Wilcox --- drivers/pci/quirks.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 48 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 4bf7102..213cad9 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -29,6 +29,7 @@ #include #include #include /* isa_dma_bridge_buggy */ +#include #include "pci.h" /* @@ -3085,11 +3086,58 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) return 0; } +#include "../gpu/drm/i915/i915_reg.h" +#define MSG_CTL 0x45010 +#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ + +static int reset_ivb_igd(struct pci_dev *dev, int probe) { + void __iomem *mmio_base; + unsigned long timeout; + u32 val; + + if (probe) + return 0; + + mmio_base = ioremap_nocache(pci_resource_start(dev, 0), + pci_resource_len(dev, 0)); + if (!mmio_base) + return -ENOMEM; + + /* Work Around */ + writel(0x00000002, mmio_base + MSG_CTL); + /* Clobbering SOUTH_CHICKEN2 register is fine only if the next + * driver loaded sets the right bits. However, this's a reset and + * the bits have been set by i915 previously, so we clobber + * SOUTH_CHICKEN2 register directly here. + */ + writel(0x00000005, mmio_base + SOUTH_CHICKEN2); + val = readl(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; + writel(val, mmio_base + PCH_PP_CONTROL); + timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); + while (time_before(jiffies, timeout)) { + val = readl(mmio_base + PCH_PP_STATUS); + if ((val & 0xB0000000) == 0) + break; + cpu_relax(); + } + writel(0x00000002, mmio_base + 0xd0100); + + iounmap(pci_resource_start(dev, 0)); + return 0; +} + #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed +#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 +#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, reset_intel_82599_sfp_virtfn }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, + reset_ivb_igd }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, + reset_ivb_igd }, { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, reset_intel_generic_dev }, { 0 } -- 1.6.0.rc1