Patchwork [30/32] target-arm: Move block cache ops to new cp15 framework

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Submitter Peter Maydell
Date April 15, 2012, 1:46 p.m.
Message ID <1334497585-867-31-git-send-email-peter.maydell@linaro.org>
Download mbox | patch
Permalink /patch/152607/
State New
Headers show

Comments

Peter Maydell - April 15, 2012, 1:46 p.m.
Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c    |   13 +++++++++++++
 target-arm/translate.c |    7 +------
 2 files changed, 14 insertions(+), 6 deletions(-)

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index ef99d1c..aef2e26 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -815,6 +815,19 @@  static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
     /* We never have a a block transfer operation in progress */
     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    /* The cache ops themselves: these all NOP for QEMU */
+    { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
+      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
+      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
+      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
     REGINFO_SENTINEL
 };
 
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6f7932f..09e2165 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2451,12 +2451,7 @@  static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
 	return 1;
 
     if ((insn & (1 << 25)) == 0) {
-        if (insn & (1 << 20)) {
-            /* mrrc */
-            return 1;
-        }
-        /* mcrr.  Used for block cache operations, so implement as no-op.  */
-        return 0;
+        return 1;
     }
     if ((insn & (1 << 4)) == 0) {
         /* cdp */