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Sat, 14 Apr 2012 18:12:57 -0400 Received: from cantor2.suse.de ([195.135.220.15]:57829 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJBDD-0000rW-DT for qemu-devel@nongnu.org; Sat, 14 Apr 2012 18:12:55 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 60D2A933A7; Sun, 15 Apr 2012 00:12:54 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sun, 15 Apr 2012 00:12:40 +0200 Message-Id: <1334441565-26433-9-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1334441565-26433-1-git-send-email-afaerber@suse.de> References: <1334441565-26433-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Subject: [Qemu-devel] [PATCH v3 08/13] target-sh4: Make find_*tlb_entry() take SuperHCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Andreas Färber --- target-sh4/helper.c | 29 +++++++++++++++-------------- 1 files changed, 15 insertions(+), 14 deletions(-) diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 2d5a4e4..d2186ed 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -243,15 +243,15 @@ static int itlb_replacement(CPUSH4State * env) /* Find the corresponding entry in the right TLB Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE */ -static int find_tlb_entry(CPUSH4State * env, target_ulong address, - tlb_t * entries, uint8_t nbtlb, int use_asid) +static int find_tlb_entry(SuperHCPU *cpu, target_ulong address, + tlb_t *entries, uint8_t nbtlb, int use_asid) { int match = MMU_DTLB_MISS; uint32_t start, end; uint8_t asid; int i; - asid = env->pteh & 0xff; + asid = cpu->env.pteh & 0xff; for (i = 0; i < nbtlb; i++) { if (!entries[i].v) @@ -304,31 +304,31 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) /* Find itlb entry Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE */ -static int find_itlb_entry(CPUSH4State * env, target_ulong address, +static int find_itlb_entry(SuperHCPU *cpu, target_ulong address, int use_asid) { int e; - e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); + e = find_tlb_entry(cpu, address, cpu->env.itlb, ITLB_SIZE, use_asid); if (e == MMU_DTLB_MULTIPLE) { e = MMU_ITLB_MULTIPLE; } else if (e == MMU_DTLB_MISS) { e = MMU_ITLB_MISS; } else if (e >= 0) { - update_itlb_use(env, e); + update_itlb_use(&cpu->env, e); } return e; } /* Find utlb entry Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ -static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid) +static int find_utlb_entry(SuperHCPU *cpu, target_ulong address, int use_asid) { /* per utlb access */ - increment_urc(sh_env_get_cpu(env)); + increment_urc(cpu); /* Return entry */ - return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); + return find_tlb_entry(cpu, address, cpu->env.utlb, UTLB_SIZE, use_asid); } /* Match address against MMU @@ -348,7 +348,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; if (rw == 2) { - n = find_itlb_entry(env, address, use_asid); + n = find_itlb_entry(sh_env_get_cpu(env), address, use_asid); if (n >= 0) { matching = &env->itlb[n]; if (!(env->sr & SR_MD) && !(matching->pr & 2)) @@ -356,7 +356,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, else *prot = PAGE_EXEC; } else { - n = find_utlb_entry(env, address, use_asid); + n = find_utlb_entry(sh_env_get_cpu(env), address, use_asid); if (n >= 0) { n = copy_utlb_entry_itlb(env, n); matching = &env->itlb[n]; @@ -375,7 +375,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, } } } else { - n = find_utlb_entry(env, address, use_asid); + n = find_utlb_entry(sh_env_get_cpu(env), address, use_asid); if (n >= 0) { matching = &env->utlb[n]; if (!(env->sr & SR_MD) && !(matching->pr & 2)) { @@ -801,6 +801,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr, int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) { + SuperHCPU *cpu = sh_env_get_cpu(env); int n; int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; @@ -832,11 +833,11 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) return 1; /* check TLB */ - n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); + n = find_tlb_entry(cpu, addr, env->itlb, ITLB_SIZE, use_asid); if (n >= 0) return env->itlb[n].c; - n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); + n = find_tlb_entry(cpu, addr, env->utlb, UTLB_SIZE, use_asid); if (n >= 0) return env->utlb[n].c;