From patchwork Sat Apr 14 22:12:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 152575 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4E5BAB7004 for ; Sun, 15 Apr 2012 08:50:39 +1000 (EST) Received: from localhost ([::1]:46292 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJBEB-0002ZO-Ek for incoming@patchwork.ozlabs.org; Sat, 14 Apr 2012 18:13:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40329) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJBDG-0000QS-Qp for qemu-devel@nongnu.org; Sat, 14 Apr 2012 18:13:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SJBDC-0000rb-N2 for qemu-devel@nongnu.org; Sat, 14 Apr 2012 18:12:58 -0400 Received: from cantor2.suse.de ([195.135.220.15]:57827 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJBDC-0000qt-Dq for qemu-devel@nongnu.org; Sat, 14 Apr 2012 18:12:54 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 61E07934B2; Sun, 15 Apr 2012 00:12:53 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sun, 15 Apr 2012 00:12:38 +0200 Message-Id: <1334441565-26433-7-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1334441565-26433-1-git-send-email-afaerber@suse.de> References: <1334441565-26433-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Subject: [Qemu-devel] [PATCH v3 06/13] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Change argument type from CPUSH4State to SuperHCPU. This simplifies the SH7750 SoC as its only caller. Signed-off-by: Andreas Färber --- hw/sh7750.c | 2 +- target-sh4/cpu.h | 2 +- target-sh4/helper.c | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/sh7750.c b/hw/sh7750.c index 23950aa..ca7839e 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -406,7 +406,7 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, return; case SH7750_MMUCR_A7: if (mem_value & MMUCR_TI) { - cpu_sh4_invalidate_tlb(&s->cpu->env); + cpu_sh4_invalidate_tlb(s->cpu); } s->cpu->env.mmucr = mem_value & ~MMUCR_TI; return; diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 6a518f2..4e0114c 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -199,7 +199,7 @@ void do_interrupt(CPUSH4State * env); void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); #if !defined(CONFIG_USER_ONLY) -void cpu_sh4_invalidate_tlb(CPUSH4State *s); +void cpu_sh4_invalidate_tlb(SuperHCPU *cpu); uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr); void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr, diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 5c57380..655faaa 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -555,22 +555,22 @@ void cpu_load_tlb(CPUSH4State * env) entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); } - void cpu_sh4_invalidate_tlb(CPUSH4State *s) +void cpu_sh4_invalidate_tlb(SuperHCPU *cpu) { int i; /* UTLB */ for (i = 0; i < UTLB_SIZE; i++) { - tlb_t * entry = &s->utlb[i]; + tlb_t *entry = &cpu->env.utlb[i]; entry->v = 0; } /* ITLB */ for (i = 0; i < ITLB_SIZE; i++) { - tlb_t * entry = &s->itlb[i]; + tlb_t *entry = &cpu->env.itlb[i]; entry->v = 0; } - tlb_flush(s, 1); + tlb_flush(&cpu->env, 1); } uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,